1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes
85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes
86 *
87 * Features supported by this driver:
88 * Software PEC no
89 * Hardware PEC yes
90 * Block buffer yes
91 * Block process call transaction yes
92 * I2C block read transaction yes (doesn't use the block buffer)
93 * Slave mode no
94 * SMBus Host Notify yes
95 * Interrupt processing yes
96 *
97 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
98 */
99
100 #define DRV_NAME "i801_smbus"
101
102 #include <linux/interrupt.h>
103 #include <linux/module.h>
104 #include <linux/pci.h>
105 #include <linux/kernel.h>
106 #include <linux/stddef.h>
107 #include <linux/delay.h>
108 #include <linux/ioport.h>
109 #include <linux/init.h>
110 #include <linux/i2c.h>
111 #include <linux/i2c-smbus.h>
112 #include <linux/acpi.h>
113 #include <linux/io.h>
114 #include <linux/dmi.h>
115 #include <linux/slab.h>
116 #include <linux/string.h>
117 #include <linux/completion.h>
118 #include <linux/err.h>
119 #include <linux/platform_device.h>
120 #include <linux/platform_data/itco_wdt.h>
121 #include <linux/platform_data/x86/p2sb.h>
122 #include <linux/pm_runtime.h>
123 #include <linux/mutex.h>
124
125 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
126 #include <linux/gpio/machine.h>
127 #include <linux/platform_data/i2c-mux-gpio.h>
128 #endif
129
130 /* I801 SMBus address offsets */
131 #define SMBHSTSTS(p) (0 + (p)->smba)
132 #define SMBHSTCNT(p) (2 + (p)->smba)
133 #define SMBHSTCMD(p) (3 + (p)->smba)
134 #define SMBHSTADD(p) (4 + (p)->smba)
135 #define SMBHSTDAT0(p) (5 + (p)->smba)
136 #define SMBHSTDAT1(p) (6 + (p)->smba)
137 #define SMBBLKDAT(p) (7 + (p)->smba)
138 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
139 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
140 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
141 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
142 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
143 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
144
145 /* PCI Address Constants */
146 #define SMBBAR 4
147 #define SMBHSTCFG 0x040
148 #define TCOBASE 0x050
149 #define TCOCTL 0x054
150
151 #define SBREG_SMBCTRL 0xc6000c
152 #define SBREG_SMBCTRL_DNV 0xcf000c
153
154 /* Host configuration bits for SMBHSTCFG */
155 #define SMBHSTCFG_HST_EN BIT(0)
156 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
157 #define SMBHSTCFG_I2C_EN BIT(2)
158 #define SMBHSTCFG_SPD_WD BIT(4)
159
160 /* TCO configuration bits for TCOCTL */
161 #define TCOCTL_EN BIT(8)
162
163 /* Auxiliary status register bits, ICH4+ only */
164 #define SMBAUXSTS_CRCE BIT(0)
165 #define SMBAUXSTS_STCO BIT(1)
166
167 /* Auxiliary control register bits, ICH4+ only */
168 #define SMBAUXCTL_CRC BIT(0)
169 #define SMBAUXCTL_E32B BIT(1)
170
171 /* I801 command constants */
172 #define I801_QUICK 0x00
173 #define I801_BYTE 0x04
174 #define I801_BYTE_DATA 0x08
175 #define I801_WORD_DATA 0x0C
176 #define I801_PROC_CALL 0x10
177 #define I801_BLOCK_DATA 0x14
178 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
179 #define I801_BLOCK_PROC_CALL 0x1C
180
181 /* I801 Host Control register bits */
182 #define SMBHSTCNT_INTREN BIT(0)
183 #define SMBHSTCNT_KILL BIT(1)
184 #define SMBHSTCNT_LAST_BYTE BIT(5)
185 #define SMBHSTCNT_START BIT(6)
186 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
187
188 /* I801 Hosts Status register bits */
189 #define SMBHSTSTS_BYTE_DONE BIT(7)
190 #define SMBHSTSTS_INUSE_STS BIT(6)
191 #define SMBHSTSTS_SMBALERT_STS BIT(5)
192 #define SMBHSTSTS_FAILED BIT(4)
193 #define SMBHSTSTS_BUS_ERR BIT(3)
194 #define SMBHSTSTS_DEV_ERR BIT(2)
195 #define SMBHSTSTS_INTR BIT(1)
196 #define SMBHSTSTS_HOST_BUSY BIT(0)
197
198 /* Host Notify Status register bits */
199 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
200
201 /* Host Notify Command register bits */
202 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
203 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
204
205 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
206 SMBHSTSTS_DEV_ERR)
207
208 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
209 STATUS_ERROR_FLAGS)
210
211 /* Older devices have their ID defined in <linux/pci_ids.h> */
212 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
213 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
214 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
215 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
216 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
217 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
218 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
220 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
221 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
222 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
223 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
224 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
225 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
226 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
227 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
228 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
229 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
230 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
231 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
232 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
233 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
234 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
235 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
237 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
238 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
239 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
240 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722
241 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
242 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
243 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
244 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
245 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
246 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
247 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
248 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
249 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
250 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
251 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
252 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
253 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
254 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
255 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
256 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
257 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
258 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
259 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
260 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
261 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
262 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
263 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322
264 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422
265
266 struct i801_mux_config {
267 char *gpio_chip;
268 unsigned values[3];
269 int n_values;
270 unsigned classes[3];
271 unsigned gpios[2]; /* Relative to gpio_chip->base */
272 int n_gpios;
273 };
274
275 struct i801_priv {
276 struct i2c_adapter adapter;
277 unsigned long smba;
278 unsigned char original_hstcfg;
279 unsigned char original_hstcnt;
280 unsigned char original_slvcmd;
281 struct pci_dev *pci_dev;
282 unsigned int features;
283
284 /* isr processing */
285 struct completion done;
286 u8 status;
287
288 /* Command state used by isr for byte-by-byte block transactions */
289 u8 cmd;
290 bool is_read;
291 int count;
292 int len;
293 u8 *data;
294
295 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
296 const struct i801_mux_config *mux_drvdata;
297 struct platform_device *mux_pdev;
298 struct gpiod_lookup_table *lookup;
299 #endif
300 struct platform_device *tco_pdev;
301
302 /*
303 * If set to true the host controller registers are reserved for
304 * ACPI AML use. Protected by acpi_lock.
305 */
306 bool acpi_reserved;
307 struct mutex acpi_lock;
308 };
309
310 #define FEATURE_SMBUS_PEC BIT(0)
311 #define FEATURE_BLOCK_BUFFER BIT(1)
312 #define FEATURE_BLOCK_PROC BIT(2)
313 #define FEATURE_I2C_BLOCK_READ BIT(3)
314 #define FEATURE_IRQ BIT(4)
315 #define FEATURE_HOST_NOTIFY BIT(5)
316 /* Not really a feature, but it's convenient to handle it as such */
317 #define FEATURE_IDF BIT(15)
318 #define FEATURE_TCO_SPT BIT(16)
319 #define FEATURE_TCO_CNL BIT(17)
320
321 static const char *i801_feature_names[] = {
322 "SMBus PEC",
323 "Block buffer",
324 "Block process call",
325 "I2C block read",
326 "Interrupt",
327 "SMBus Host Notify",
328 };
329
330 static unsigned int disable_features;
331 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
332 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
333 "\t\t 0x01 disable SMBus PEC\n"
334 "\t\t 0x02 disable the block buffer\n"
335 "\t\t 0x08 disable the I2C block read functionality\n"
336 "\t\t 0x10 don't use interrupts\n"
337 "\t\t 0x20 disable SMBus Host Notify ");
338
339 /* Make sure the SMBus host is ready to start transmitting.
340 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)341 static int i801_check_pre(struct i801_priv *priv)
342 {
343 int status;
344
345 status = inb_p(SMBHSTSTS(priv));
346 if (status & SMBHSTSTS_HOST_BUSY) {
347 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
348 return -EBUSY;
349 }
350
351 status &= STATUS_FLAGS;
352 if (status) {
353 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
354 outb_p(status, SMBHSTSTS(priv));
355 }
356
357 /*
358 * Clear CRC status if needed.
359 * During normal operation, i801_check_post() takes care
360 * of it after every operation. We do it here only in case
361 * the hardware was already in this state when the driver
362 * started.
363 */
364 if (priv->features & FEATURE_SMBUS_PEC) {
365 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
366 if (status) {
367 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
368 outb_p(status, SMBAUXSTS(priv));
369 }
370 }
371
372 return 0;
373 }
374
i801_check_post(struct i801_priv * priv,int status)375 static int i801_check_post(struct i801_priv *priv, int status)
376 {
377 int result = 0;
378
379 /*
380 * If the SMBus is still busy, we give up
381 */
382 if (unlikely(status < 0)) {
383 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
384 /* try to stop the current command */
385 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
386 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
387 usleep_range(1000, 2000);
388 outb_p(0, SMBHSTCNT(priv));
389
390 /* Check if it worked */
391 status = inb_p(SMBHSTSTS(priv));
392 if ((status & SMBHSTSTS_HOST_BUSY) ||
393 !(status & SMBHSTSTS_FAILED))
394 dev_err(&priv->pci_dev->dev,
395 "Failed terminating the transaction\n");
396 return -ETIMEDOUT;
397 }
398
399 if (status & SMBHSTSTS_FAILED) {
400 result = -EIO;
401 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
402 }
403 if (status & SMBHSTSTS_DEV_ERR) {
404 /*
405 * This may be a PEC error, check and clear it.
406 *
407 * AUXSTS is handled differently from HSTSTS.
408 * For HSTSTS, i801_isr() or i801_wait_intr()
409 * has already cleared the error bits in hardware,
410 * and we are passed a copy of the original value
411 * in "status".
412 * For AUXSTS, the hardware register is left
413 * for us to handle here.
414 * This is asymmetric, slightly iffy, but safe,
415 * since all this code is serialized and the CRCE
416 * bit is harmless as long as it's cleared before
417 * the next operation.
418 */
419 if ((priv->features & FEATURE_SMBUS_PEC) &&
420 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
421 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
422 result = -EBADMSG;
423 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
424 } else {
425 result = -ENXIO;
426 dev_dbg(&priv->pci_dev->dev, "No response\n");
427 }
428 }
429 if (status & SMBHSTSTS_BUS_ERR) {
430 result = -EAGAIN;
431 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
432 }
433
434 return result;
435 }
436
437 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)438 static int i801_wait_intr(struct i801_priv *priv)
439 {
440 unsigned long timeout = jiffies + priv->adapter.timeout;
441 int status, busy;
442
443 do {
444 usleep_range(250, 500);
445 status = inb_p(SMBHSTSTS(priv));
446 busy = status & SMBHSTSTS_HOST_BUSY;
447 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
448 if (!busy && status)
449 return status & STATUS_ERROR_FLAGS;
450 } while (time_is_after_eq_jiffies(timeout));
451
452 return -ETIMEDOUT;
453 }
454
455 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)456 static int i801_wait_byte_done(struct i801_priv *priv)
457 {
458 unsigned long timeout = jiffies + priv->adapter.timeout;
459 int status;
460
461 do {
462 usleep_range(250, 500);
463 status = inb_p(SMBHSTSTS(priv));
464 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
465 return status & STATUS_ERROR_FLAGS;
466 } while (time_is_after_eq_jiffies(timeout));
467
468 return -ETIMEDOUT;
469 }
470
i801_transaction(struct i801_priv * priv,int xact)471 static int i801_transaction(struct i801_priv *priv, int xact)
472 {
473 unsigned long result;
474 const struct i2c_adapter *adap = &priv->adapter;
475
476 if (priv->features & FEATURE_IRQ) {
477 reinit_completion(&priv->done);
478 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
479 SMBHSTCNT(priv));
480 result = wait_for_completion_timeout(&priv->done, adap->timeout);
481 return result ? priv->status : -ETIMEDOUT;
482 }
483
484 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
485
486 return i801_wait_intr(priv);
487 }
488
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)489 static int i801_block_transaction_by_block(struct i801_priv *priv,
490 union i2c_smbus_data *data,
491 char read_write, int command)
492 {
493 int i, len, status, xact;
494
495 switch (command) {
496 case I2C_SMBUS_BLOCK_PROC_CALL:
497 xact = I801_BLOCK_PROC_CALL;
498 break;
499 case I2C_SMBUS_BLOCK_DATA:
500 xact = I801_BLOCK_DATA;
501 break;
502 default:
503 return -EOPNOTSUPP;
504 }
505
506 /* Set block buffer mode */
507 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
508
509 if (read_write == I2C_SMBUS_WRITE) {
510 len = data->block[0];
511 outb_p(len, SMBHSTDAT0(priv));
512 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
513 for (i = 0; i < len; i++)
514 outb_p(data->block[i+1], SMBBLKDAT(priv));
515 }
516
517 status = i801_transaction(priv, xact);
518 if (status)
519 goto out;
520
521 if (read_write == I2C_SMBUS_READ ||
522 command == I2C_SMBUS_BLOCK_PROC_CALL) {
523 len = inb_p(SMBHSTDAT0(priv));
524 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
525 status = -EPROTO;
526 goto out;
527 }
528
529 data->block[0] = len;
530 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
531 for (i = 0; i < len; i++)
532 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
533 }
534 out:
535 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
536 return status;
537 }
538
i801_isr_byte_done(struct i801_priv * priv)539 static void i801_isr_byte_done(struct i801_priv *priv)
540 {
541 if (priv->is_read) {
542 /* For SMBus block reads, length is received with first byte */
543 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
544 (priv->count == 0)) {
545 priv->len = inb_p(SMBHSTDAT0(priv));
546 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
547 dev_err(&priv->pci_dev->dev,
548 "Illegal SMBus block read size %d\n",
549 priv->len);
550 /* FIXME: Recover */
551 priv->len = I2C_SMBUS_BLOCK_MAX;
552 }
553 priv->data[-1] = priv->len;
554 }
555
556 /* Read next byte */
557 if (priv->count < priv->len)
558 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
559 else
560 dev_dbg(&priv->pci_dev->dev,
561 "Discarding extra byte on block read\n");
562
563 /* Set LAST_BYTE for last byte of read transaction */
564 if (priv->count == priv->len - 1)
565 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
566 SMBHSTCNT(priv));
567 } else if (priv->count < priv->len - 1) {
568 /* Write next byte, except for IRQ after last byte */
569 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
570 }
571 }
572
i801_host_notify_isr(struct i801_priv * priv)573 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
574 {
575 unsigned short addr;
576
577 addr = inb_p(SMBNTFDADD(priv)) >> 1;
578
579 /*
580 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
581 * always returns 0. Our current implementation doesn't provide
582 * data, so we just ignore it.
583 */
584 i2c_handle_smbus_host_notify(&priv->adapter, addr);
585
586 /* clear Host Notify bit and return */
587 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
588 return IRQ_HANDLED;
589 }
590
591 /*
592 * There are three kinds of interrupts:
593 *
594 * 1) i801 signals transaction completion with one of these interrupts:
595 * INTR - Success
596 * DEV_ERR - Invalid command, NAK or communication timeout
597 * BUS_ERR - SMI# transaction collision
598 * FAILED - transaction was canceled due to a KILL request
599 * When any of these occur, update ->status and signal completion.
600 *
601 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
602 * occurs for each byte of a byte-by-byte to prepare the next byte.
603 *
604 * 3) Host Notify interrupts
605 */
i801_isr(int irq,void * dev_id)606 static irqreturn_t i801_isr(int irq, void *dev_id)
607 {
608 struct i801_priv *priv = dev_id;
609 u16 pcists;
610 u8 status;
611
612 /* Confirm this is our interrupt */
613 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
614 if (!(pcists & PCI_STATUS_INTERRUPT))
615 return IRQ_NONE;
616
617 if (priv->features & FEATURE_HOST_NOTIFY) {
618 status = inb_p(SMBSLVSTS(priv));
619 if (status & SMBSLVSTS_HST_NTFY_STS)
620 return i801_host_notify_isr(priv);
621 }
622
623 status = inb_p(SMBHSTSTS(priv));
624 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
625 i801_isr_byte_done(priv);
626
627 /*
628 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
629 * independently of the interrupt generation being blocked or not
630 * so clear it always when the status is set.
631 */
632 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
633 outb_p(status, SMBHSTSTS(priv));
634
635 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
636 if (status) {
637 priv->status = status & STATUS_ERROR_FLAGS;
638 complete(&priv->done);
639 }
640
641 return IRQ_HANDLED;
642 }
643
644 /*
645 * For "byte-by-byte" block transactions:
646 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
647 * I2C read uses cmd=I801_I2C_BLOCK_DATA
648 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)649 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
650 union i2c_smbus_data *data,
651 char read_write, int command)
652 {
653 int i, len;
654 int smbcmd;
655 int status;
656 unsigned long result;
657 const struct i2c_adapter *adap = &priv->adapter;
658
659 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
660 return -EOPNOTSUPP;
661
662 len = data->block[0];
663
664 if (read_write == I2C_SMBUS_WRITE) {
665 outb_p(len, SMBHSTDAT0(priv));
666 outb_p(data->block[1], SMBBLKDAT(priv));
667 }
668
669 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
670 read_write == I2C_SMBUS_READ)
671 smbcmd = I801_I2C_BLOCK_DATA;
672 else
673 smbcmd = I801_BLOCK_DATA;
674
675 if (priv->features & FEATURE_IRQ) {
676 priv->is_read = (read_write == I2C_SMBUS_READ);
677 if (len == 1 && priv->is_read)
678 smbcmd |= SMBHSTCNT_LAST_BYTE;
679 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
680 priv->len = len;
681 priv->count = 0;
682 priv->data = &data->block[1];
683
684 reinit_completion(&priv->done);
685 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
686 result = wait_for_completion_timeout(&priv->done, adap->timeout);
687 return result ? priv->status : -ETIMEDOUT;
688 }
689
690 if (len == 1 && read_write == I2C_SMBUS_READ)
691 smbcmd |= SMBHSTCNT_LAST_BYTE;
692 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
693
694 for (i = 1; i <= len; i++) {
695 status = i801_wait_byte_done(priv);
696 if (status)
697 return status;
698
699 if (i == 1 && read_write == I2C_SMBUS_READ
700 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
701 len = inb_p(SMBHSTDAT0(priv));
702 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
703 dev_err(&priv->pci_dev->dev,
704 "Illegal SMBus block read size %d\n",
705 len);
706 /* Recover */
707 while (inb_p(SMBHSTSTS(priv)) &
708 SMBHSTSTS_HOST_BUSY)
709 outb_p(SMBHSTSTS_BYTE_DONE,
710 SMBHSTSTS(priv));
711 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
712 return -EPROTO;
713 }
714 data->block[0] = len;
715 }
716
717 if (read_write == I2C_SMBUS_READ) {
718 data->block[i] = inb_p(SMBBLKDAT(priv));
719 if (i == len - 1)
720 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
721 }
722
723 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
724 outb_p(data->block[i+1], SMBBLKDAT(priv));
725
726 /* signals SMBBLKDAT ready */
727 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
728 }
729
730 return i801_wait_intr(priv);
731 }
732
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)733 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
734 {
735 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
736 }
737
738 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)739 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
740 u8 addr, u8 hstcmd, char read_write, int command)
741 {
742 int xact, ret;
743
744 switch (command) {
745 case I2C_SMBUS_QUICK:
746 i801_set_hstadd(priv, addr, read_write);
747 xact = I801_QUICK;
748 break;
749 case I2C_SMBUS_BYTE:
750 i801_set_hstadd(priv, addr, read_write);
751 if (read_write == I2C_SMBUS_WRITE)
752 outb_p(hstcmd, SMBHSTCMD(priv));
753 xact = I801_BYTE;
754 break;
755 case I2C_SMBUS_BYTE_DATA:
756 i801_set_hstadd(priv, addr, read_write);
757 if (read_write == I2C_SMBUS_WRITE)
758 outb_p(data->byte, SMBHSTDAT0(priv));
759 outb_p(hstcmd, SMBHSTCMD(priv));
760 xact = I801_BYTE_DATA;
761 break;
762 case I2C_SMBUS_WORD_DATA:
763 i801_set_hstadd(priv, addr, read_write);
764 if (read_write == I2C_SMBUS_WRITE) {
765 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
766 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
767 }
768 outb_p(hstcmd, SMBHSTCMD(priv));
769 xact = I801_WORD_DATA;
770 break;
771 case I2C_SMBUS_PROC_CALL:
772 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
773 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
774 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
775 outb_p(hstcmd, SMBHSTCMD(priv));
776 read_write = I2C_SMBUS_READ;
777 xact = I801_PROC_CALL;
778 break;
779 default:
780 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
781 return -EOPNOTSUPP;
782 }
783
784 ret = i801_transaction(priv, xact);
785 if (ret || read_write == I2C_SMBUS_WRITE)
786 return ret;
787
788 switch (command) {
789 case I2C_SMBUS_BYTE:
790 case I2C_SMBUS_BYTE_DATA:
791 data->byte = inb_p(SMBHSTDAT0(priv));
792 break;
793 case I2C_SMBUS_WORD_DATA:
794 case I2C_SMBUS_PROC_CALL:
795 data->word = inb_p(SMBHSTDAT0(priv)) +
796 (inb_p(SMBHSTDAT1(priv)) << 8);
797 break;
798 }
799
800 return 0;
801 }
802
803 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)804 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
805 u8 addr, u8 hstcmd, char read_write, int command)
806 {
807 int result = 0;
808 unsigned char hostc;
809
810 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
811 data->block[0] = I2C_SMBUS_BLOCK_MAX;
812 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
813 return -EPROTO;
814
815 switch (command) {
816 case I2C_SMBUS_BLOCK_DATA:
817 i801_set_hstadd(priv, addr, read_write);
818 outb_p(hstcmd, SMBHSTCMD(priv));
819 break;
820 case I2C_SMBUS_I2C_BLOCK_DATA:
821 /*
822 * NB: page 240 of ICH5 datasheet shows that the R/#W
823 * bit should be cleared here, even when reading.
824 * However if SPD Write Disable is set (Lynx Point and later),
825 * the read will fail if we don't set the R/#W bit.
826 */
827 i801_set_hstadd(priv, addr,
828 priv->original_hstcfg & SMBHSTCFG_SPD_WD ?
829 read_write : I2C_SMBUS_WRITE);
830 if (read_write == I2C_SMBUS_READ) {
831 /* NB: page 240 of ICH5 datasheet also shows
832 * that DATA1 is the cmd field when reading
833 */
834 outb_p(hstcmd, SMBHSTDAT1(priv));
835 } else
836 outb_p(hstcmd, SMBHSTCMD(priv));
837
838 if (read_write == I2C_SMBUS_WRITE) {
839 /* set I2C_EN bit in configuration register */
840 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
841 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
842 hostc | SMBHSTCFG_I2C_EN);
843 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
844 dev_err(&priv->pci_dev->dev,
845 "I2C block read is unsupported!\n");
846 return -EOPNOTSUPP;
847 }
848 break;
849 case I2C_SMBUS_BLOCK_PROC_CALL:
850 /* Needs to be flagged as write transaction */
851 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
852 outb_p(hstcmd, SMBHSTCMD(priv));
853 break;
854 }
855
856 /* Experience has shown that the block buffer can only be used for
857 SMBus (not I2C) block transactions, even though the datasheet
858 doesn't mention this limitation. */
859 if ((priv->features & FEATURE_BLOCK_BUFFER) &&
860 command != I2C_SMBUS_I2C_BLOCK_DATA)
861 result = i801_block_transaction_by_block(priv, data,
862 read_write,
863 command);
864 else
865 result = i801_block_transaction_byte_by_byte(priv, data,
866 read_write,
867 command);
868
869 if (command == I2C_SMBUS_I2C_BLOCK_DATA
870 && read_write == I2C_SMBUS_WRITE) {
871 /* restore saved configuration register value */
872 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
873 }
874 return result;
875 }
876
877 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)878 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
879 unsigned short flags, char read_write, u8 command,
880 int size, union i2c_smbus_data *data)
881 {
882 int hwpec, ret;
883 struct i801_priv *priv = i2c_get_adapdata(adap);
884
885 mutex_lock(&priv->acpi_lock);
886 if (priv->acpi_reserved) {
887 mutex_unlock(&priv->acpi_lock);
888 return -EBUSY;
889 }
890
891 pm_runtime_get_sync(&priv->pci_dev->dev);
892
893 ret = i801_check_pre(priv);
894 if (ret)
895 goto out;
896
897 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
898 && size != I2C_SMBUS_QUICK
899 && size != I2C_SMBUS_I2C_BLOCK_DATA;
900
901 if (hwpec) /* enable/disable hardware PEC */
902 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
903 else
904 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
905 SMBAUXCTL(priv));
906
907 if (size == I2C_SMBUS_BLOCK_DATA ||
908 size == I2C_SMBUS_I2C_BLOCK_DATA ||
909 size == I2C_SMBUS_BLOCK_PROC_CALL)
910 ret = i801_block_transaction(priv, data, addr, command, read_write, size);
911 else
912 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
913
914 ret = i801_check_post(priv, ret);
915
916 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
917 * time, so we forcibly disable it after every transaction.
918 */
919 if (hwpec)
920 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
921 out:
922 /*
923 * Unlock the SMBus device for use by BIOS/ACPI,
924 * and clear status flags if not done already.
925 */
926 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
927
928 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
929 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
930 mutex_unlock(&priv->acpi_lock);
931 return ret;
932 }
933
934
i801_func(struct i2c_adapter * adapter)935 static u32 i801_func(struct i2c_adapter *adapter)
936 {
937 struct i801_priv *priv = i2c_get_adapdata(adapter);
938
939 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
940 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
941 I2C_FUNC_SMBUS_PROC_CALL |
942 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
943 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
944 ((priv->features & FEATURE_BLOCK_PROC) ?
945 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
946 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
947 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
948 ((priv->features & FEATURE_HOST_NOTIFY) ?
949 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
950 }
951
i801_enable_host_notify(struct i2c_adapter * adapter)952 static void i801_enable_host_notify(struct i2c_adapter *adapter)
953 {
954 struct i801_priv *priv = i2c_get_adapdata(adapter);
955
956 if (!(priv->features & FEATURE_HOST_NOTIFY))
957 return;
958
959 /*
960 * Enable host notify interrupt and block the generation of interrupt
961 * from the SMB_ALERT signal because the driver does not support
962 * SMBus Alert.
963 */
964 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
965 priv->original_slvcmd, SMBSLVCMD(priv));
966
967 /* clear Host Notify bit to allow a new notification */
968 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
969 }
970
i801_disable_host_notify(struct i801_priv * priv)971 static void i801_disable_host_notify(struct i801_priv *priv)
972 {
973 if (!(priv->features & FEATURE_HOST_NOTIFY))
974 return;
975
976 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
977 }
978
979 static const struct i2c_algorithm smbus_algorithm = {
980 .smbus_xfer = i801_access,
981 .functionality = i801_func,
982 };
983
984 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \
985 FEATURE_IRQ | FEATURE_SMBUS_PEC | \
986 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
987 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
988 FEATURE_HOST_NOTIFY)
989
990 static const struct pci_device_id i801_ids[] = {
991 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
992 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
993 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
994 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
995 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
996 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
997 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
998 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
999 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
1000 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
1001 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
1002 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
1004 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
1005 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1006 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1012 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1013 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1014 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1015 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1016 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1017 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1018 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1021 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1022 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1023 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1024 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1025 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1026 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1027 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1028 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1029 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1030 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1031 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1033 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1036 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1037 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1043 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058 { 0, }
1059 };
1060
1061 MODULE_DEVICE_TABLE(pci, i801_ids);
1062
1063 #if defined CONFIG_X86 && defined CONFIG_DMI
1064 static unsigned char apanel_addr __ro_after_init;
1065
1066 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1067 static __init const void __iomem *bios_signature(const void __iomem *bios)
1068 {
1069 ssize_t offset;
1070 const unsigned char signature[] = "FJKEYINF";
1071
1072 for (offset = 0; offset < 0x10000; offset += 0x10) {
1073 if (check_signature(bios + offset, signature,
1074 sizeof(signature)-1))
1075 return bios + offset;
1076 }
1077 return NULL;
1078 }
1079
input_apanel_init(void)1080 static void __init input_apanel_init(void)
1081 {
1082 void __iomem *bios;
1083 const void __iomem *p;
1084
1085 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1086 p = bios_signature(bios);
1087 if (p) {
1088 /* just use the first address */
1089 apanel_addr = readb(p + 8 + 3) >> 1;
1090 }
1091 iounmap(bios);
1092 }
1093
1094 struct dmi_onboard_device_info {
1095 const char *name;
1096 u8 type;
1097 unsigned short i2c_addr;
1098 const char *i2c_type;
1099 };
1100
1101 static const struct dmi_onboard_device_info dmi_devices[] = {
1102 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1103 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1104 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1105 };
1106
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1107 static void dmi_check_onboard_device(u8 type, const char *name,
1108 struct i2c_adapter *adap)
1109 {
1110 int i;
1111 struct i2c_board_info info;
1112
1113 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1114 /* & ~0x80, ignore enabled/disabled bit */
1115 if ((type & ~0x80) != dmi_devices[i].type)
1116 continue;
1117 if (strcasecmp(name, dmi_devices[i].name))
1118 continue;
1119
1120 memset(&info, 0, sizeof(struct i2c_board_info));
1121 info.addr = dmi_devices[i].i2c_addr;
1122 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1123 i2c_new_client_device(adap, &info);
1124 break;
1125 }
1126 }
1127
1128 /* We use our own function to check for onboard devices instead of
1129 dmi_find_device() as some buggy BIOS's have the devices we are interested
1130 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1131 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1132 {
1133 int i, count;
1134
1135 if (dm->type != 10)
1136 return;
1137
1138 count = (dm->length - sizeof(struct dmi_header)) / 2;
1139 for (i = 0; i < count; i++) {
1140 const u8 *d = (char *)(dm + 1) + (i * 2);
1141 const char *name = ((char *) dm) + dm->length;
1142 u8 type = d[0];
1143 u8 s = d[1];
1144
1145 if (!s)
1146 continue;
1147 s--;
1148 while (s > 0 && name[0]) {
1149 name += strlen(name) + 1;
1150 s--;
1151 }
1152 if (name[0] == 0) /* Bogus string reference */
1153 continue;
1154
1155 dmi_check_onboard_device(type, name, adap);
1156 }
1157 }
1158
1159 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1160 static const char *const acpi_smo8800_ids[] = {
1161 "SMO8800",
1162 "SMO8801",
1163 "SMO8810",
1164 "SMO8811",
1165 "SMO8820",
1166 "SMO8821",
1167 "SMO8830",
1168 "SMO8831",
1169 };
1170
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1171 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1172 u32 nesting_level,
1173 void *context,
1174 void **return_value)
1175 {
1176 struct acpi_device_info *info;
1177 acpi_status status;
1178 char *hid;
1179 int i;
1180
1181 status = acpi_get_object_info(obj_handle, &info);
1182 if (ACPI_FAILURE(status))
1183 return AE_OK;
1184
1185 if (!(info->valid & ACPI_VALID_HID))
1186 goto smo88xx_not_found;
1187
1188 hid = info->hardware_id.string;
1189 if (!hid)
1190 goto smo88xx_not_found;
1191
1192 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1193 if (i < 0)
1194 goto smo88xx_not_found;
1195
1196 kfree(info);
1197
1198 *return_value = NULL;
1199 return AE_CTRL_TERMINATE;
1200
1201 smo88xx_not_found:
1202 kfree(info);
1203 return AE_OK;
1204 }
1205
is_dell_system_with_lis3lv02d(void)1206 static bool is_dell_system_with_lis3lv02d(void)
1207 {
1208 void *err = ERR_PTR(-ENOENT);
1209
1210 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1211 return false;
1212
1213 /*
1214 * Check that ACPI device SMO88xx is present and is functioning.
1215 * Function acpi_get_devices() already filters all ACPI devices
1216 * which are not present or are not functioning.
1217 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1218 * accelerometer but unfortunately ACPI does not provide any other
1219 * information (like I2C address).
1220 */
1221 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1222
1223 return !IS_ERR(err);
1224 }
1225
1226 /*
1227 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1228 * so it is needed to define mapping table based on DMI product names.
1229 */
1230 static const struct {
1231 const char *dmi_product_name;
1232 unsigned short i2c_addr;
1233 } dell_lis3lv02d_devices[] = {
1234 /*
1235 * Dell platform team told us that these Latitude devices have
1236 * ST microelectronics accelerometer at I2C address 0x29.
1237 */
1238 { "Latitude E5250", 0x29 },
1239 { "Latitude E5450", 0x29 },
1240 { "Latitude E5550", 0x29 },
1241 { "Latitude E6440", 0x29 },
1242 { "Latitude E6440 ATG", 0x29 },
1243 { "Latitude E6540", 0x29 },
1244 /*
1245 * Additional individual entries were added after verification.
1246 */
1247 { "Latitude 5480", 0x29 },
1248 { "Vostro V131", 0x1d },
1249 { "Vostro 5568", 0x29 },
1250 };
1251
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1252 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1253 {
1254 struct i2c_board_info info;
1255 const char *dmi_product_name;
1256 int i;
1257
1258 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1259 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1260 if (strcmp(dmi_product_name,
1261 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1262 break;
1263 }
1264
1265 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1266 dev_warn(&priv->pci_dev->dev,
1267 "Accelerometer lis3lv02d is present on SMBus but its"
1268 " address is unknown, skipping registration\n");
1269 return;
1270 }
1271
1272 memset(&info, 0, sizeof(struct i2c_board_info));
1273 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1274 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1275 i2c_new_client_device(&priv->adapter, &info);
1276 }
1277
1278 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1279 static void i801_probe_optional_slaves(struct i801_priv *priv)
1280 {
1281 /* Only register slaves on main SMBus channel */
1282 if (priv->features & FEATURE_IDF)
1283 return;
1284
1285 if (apanel_addr) {
1286 struct i2c_board_info info = {
1287 .addr = apanel_addr,
1288 .type = "fujitsu_apanel",
1289 };
1290
1291 i2c_new_client_device(&priv->adapter, &info);
1292 }
1293
1294 if (dmi_name_in_vendors("FUJITSU"))
1295 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1296
1297 if (is_dell_system_with_lis3lv02d())
1298 register_dell_lis3lv02d_i2c_device(priv);
1299
1300 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1301 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1302 if (!priv->mux_drvdata)
1303 #endif
1304 i2c_register_spd(&priv->adapter);
1305 }
1306 #else
input_apanel_init(void)1307 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1308 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1309 #endif /* CONFIG_X86 && CONFIG_DMI */
1310
1311 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1312 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1313 .gpio_chip = "gpio_ich",
1314 .values = { 0x02, 0x03 },
1315 .n_values = 2,
1316 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1317 .gpios = { 52, 53 },
1318 .n_gpios = 2,
1319 };
1320
1321 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1322 .gpio_chip = "gpio_ich",
1323 .values = { 0x02, 0x03, 0x01 },
1324 .n_values = 3,
1325 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1326 .gpios = { 52, 53 },
1327 .n_gpios = 2,
1328 };
1329
1330 static const struct dmi_system_id mux_dmi_table[] = {
1331 {
1332 .matches = {
1333 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1334 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1335 },
1336 .driver_data = &i801_mux_config_asus_z8_d12,
1337 },
1338 {
1339 .matches = {
1340 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1341 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1342 },
1343 .driver_data = &i801_mux_config_asus_z8_d12,
1344 },
1345 {
1346 .matches = {
1347 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1348 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1349 },
1350 .driver_data = &i801_mux_config_asus_z8_d12,
1351 },
1352 {
1353 .matches = {
1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1355 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1356 },
1357 .driver_data = &i801_mux_config_asus_z8_d12,
1358 },
1359 {
1360 .matches = {
1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1362 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1363 },
1364 .driver_data = &i801_mux_config_asus_z8_d12,
1365 },
1366 {
1367 .matches = {
1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1370 },
1371 .driver_data = &i801_mux_config_asus_z8_d12,
1372 },
1373 {
1374 .matches = {
1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1377 },
1378 .driver_data = &i801_mux_config_asus_z8_d18,
1379 },
1380 {
1381 .matches = {
1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1384 },
1385 .driver_data = &i801_mux_config_asus_z8_d18,
1386 },
1387 {
1388 .matches = {
1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1391 },
1392 .driver_data = &i801_mux_config_asus_z8_d12,
1393 },
1394 { }
1395 };
1396
1397 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1398 static void i801_add_mux(struct i801_priv *priv)
1399 {
1400 struct device *dev = &priv->adapter.dev;
1401 const struct i801_mux_config *mux_config;
1402 struct i2c_mux_gpio_platform_data gpio_data;
1403 struct gpiod_lookup_table *lookup;
1404 int i;
1405
1406 if (!priv->mux_drvdata)
1407 return;
1408 mux_config = priv->mux_drvdata;
1409
1410 /* Prepare the platform data */
1411 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1412 gpio_data.parent = priv->adapter.nr;
1413 gpio_data.values = mux_config->values;
1414 gpio_data.n_values = mux_config->n_values;
1415 gpio_data.classes = mux_config->classes;
1416 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1417
1418 /* Register GPIO descriptor lookup table */
1419 lookup = devm_kzalloc(dev,
1420 struct_size(lookup, table, mux_config->n_gpios + 1),
1421 GFP_KERNEL);
1422 if (!lookup)
1423 return;
1424 lookup->dev_id = "i2c-mux-gpio";
1425 for (i = 0; i < mux_config->n_gpios; i++)
1426 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1427 mux_config->gpios[i], "mux", 0);
1428 gpiod_add_lookup_table(lookup);
1429
1430 /*
1431 * Register the mux device, we use PLATFORM_DEVID_NONE here
1432 * because since we are referring to the GPIO chip by name we are
1433 * anyways in deep trouble if there is more than one of these
1434 * devices, and there should likely only be one platform controller
1435 * hub.
1436 */
1437 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1438 PLATFORM_DEVID_NONE, &gpio_data,
1439 sizeof(struct i2c_mux_gpio_platform_data));
1440 if (IS_ERR(priv->mux_pdev)) {
1441 gpiod_remove_lookup_table(lookup);
1442 devm_kfree(dev, lookup);
1443 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1444 } else {
1445 priv->lookup = lookup;
1446 }
1447 }
1448
i801_del_mux(struct i801_priv * priv)1449 static void i801_del_mux(struct i801_priv *priv)
1450 {
1451 platform_device_unregister(priv->mux_pdev);
1452 gpiod_remove_lookup_table(priv->lookup);
1453 }
1454
i801_get_adapter_class(struct i801_priv * priv)1455 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1456 {
1457 const struct dmi_system_id *id;
1458 const struct i801_mux_config *mux_config;
1459 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1460 int i;
1461
1462 id = dmi_first_match(mux_dmi_table);
1463 if (id) {
1464 /* Remove branch classes from trunk */
1465 mux_config = id->driver_data;
1466 for (i = 0; i < mux_config->n_values; i++)
1467 class &= ~mux_config->classes[i];
1468
1469 /* Remember for later */
1470 priv->mux_drvdata = mux_config;
1471 }
1472
1473 return class;
1474 }
1475 #else
i801_add_mux(struct i801_priv * priv)1476 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1477 static inline void i801_del_mux(struct i801_priv *priv) { }
1478
i801_get_adapter_class(struct i801_priv * priv)1479 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1480 {
1481 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1482 }
1483 #endif
1484
1485 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1486 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1487 struct resource *tco_res)
1488 {
1489 static const struct itco_wdt_platform_data pldata = {
1490 .name = "Intel PCH",
1491 .version = 4,
1492 };
1493 struct resource *res;
1494 int ret;
1495
1496 /*
1497 * We must access the NO_REBOOT bit over the Primary to Sideband
1498 * (P2SB) bridge.
1499 */
1500
1501 res = &tco_res[1];
1502 ret = p2sb_bar(pci_dev->bus, 0, res);
1503 if (ret)
1504 return ERR_PTR(ret);
1505
1506 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1507 res->start += SBREG_SMBCTRL_DNV;
1508 else
1509 res->start += SBREG_SMBCTRL;
1510
1511 res->end = res->start + 3;
1512
1513 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1514 tco_res, 2, &pldata, sizeof(pldata));
1515 }
1516
1517 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1518 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1519 struct resource *tco_res)
1520 {
1521 static const struct itco_wdt_platform_data pldata = {
1522 .name = "Intel PCH",
1523 .version = 6,
1524 };
1525
1526 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1527 tco_res, 1, &pldata, sizeof(pldata));
1528 }
1529
i801_add_tco(struct i801_priv * priv)1530 static void i801_add_tco(struct i801_priv *priv)
1531 {
1532 struct pci_dev *pci_dev = priv->pci_dev;
1533 struct resource tco_res[2], *res;
1534 u32 tco_base, tco_ctl;
1535
1536 /* If we have ACPI based watchdog use that instead */
1537 if (acpi_has_watchdog())
1538 return;
1539
1540 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1541 return;
1542
1543 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1544 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1545 if (!(tco_ctl & TCOCTL_EN))
1546 return;
1547
1548 memset(tco_res, 0, sizeof(tco_res));
1549 /*
1550 * Always populate the main iTCO IO resource here. The second entry
1551 * for NO_REBOOT MMIO is filled by the SPT specific function.
1552 */
1553 res = &tco_res[0];
1554 res->start = tco_base & ~1;
1555 res->end = res->start + 32 - 1;
1556 res->flags = IORESOURCE_IO;
1557
1558 if (priv->features & FEATURE_TCO_CNL)
1559 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1560 else
1561 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1562
1563 if (IS_ERR(priv->tco_pdev))
1564 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1565 }
1566
1567 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1568 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1569 acpi_physical_address address)
1570 {
1571 return address >= priv->smba &&
1572 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1573 }
1574
1575 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1576 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1577 u64 *value, void *handler_context, void *region_context)
1578 {
1579 struct i801_priv *priv = handler_context;
1580 struct pci_dev *pdev = priv->pci_dev;
1581 acpi_status status;
1582
1583 /*
1584 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1585 * further access from the driver itself. This device is now owned
1586 * by the system firmware.
1587 */
1588 mutex_lock(&priv->acpi_lock);
1589
1590 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1591 priv->acpi_reserved = true;
1592
1593 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1594 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1595
1596 /*
1597 * BIOS is accessing the host controller so prevent it from
1598 * suspending automatically from now on.
1599 */
1600 pm_runtime_get_sync(&pdev->dev);
1601 }
1602
1603 if ((function & ACPI_IO_MASK) == ACPI_READ)
1604 status = acpi_os_read_port(address, (u32 *)value, bits);
1605 else
1606 status = acpi_os_write_port(address, (u32)*value, bits);
1607
1608 mutex_unlock(&priv->acpi_lock);
1609
1610 return status;
1611 }
1612
i801_acpi_probe(struct i801_priv * priv)1613 static int i801_acpi_probe(struct i801_priv *priv)
1614 {
1615 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1616 acpi_status status;
1617
1618 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1619 i801_acpi_io_handler, NULL, priv);
1620 if (ACPI_SUCCESS(status))
1621 return 0;
1622
1623 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1624 }
1625
i801_acpi_remove(struct i801_priv * priv)1626 static void i801_acpi_remove(struct i801_priv *priv)
1627 {
1628 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1629
1630 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1631 }
1632 #else
i801_acpi_probe(struct i801_priv * priv)1633 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1634 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1635 #endif
1636
i801_setup_hstcfg(struct i801_priv * priv)1637 static void i801_setup_hstcfg(struct i801_priv *priv)
1638 {
1639 unsigned char hstcfg = priv->original_hstcfg;
1640
1641 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1642 hstcfg |= SMBHSTCFG_HST_EN;
1643 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1644 }
1645
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1646 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1647 {
1648 int err, i;
1649 struct i801_priv *priv;
1650
1651 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1652 if (!priv)
1653 return -ENOMEM;
1654
1655 i2c_set_adapdata(&priv->adapter, priv);
1656 priv->adapter.owner = THIS_MODULE;
1657 priv->adapter.class = i801_get_adapter_class(priv);
1658 priv->adapter.algo = &smbus_algorithm;
1659 priv->adapter.dev.parent = &dev->dev;
1660 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1661 priv->adapter.retries = 3;
1662 mutex_init(&priv->acpi_lock);
1663
1664 priv->pci_dev = dev;
1665 priv->features = id->driver_data;
1666
1667 /* Disable features on user request */
1668 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1669 if (priv->features & disable_features & (1 << i))
1670 dev_notice(&dev->dev, "%s disabled by user\n",
1671 i801_feature_names[i]);
1672 }
1673 priv->features &= ~disable_features;
1674
1675 /* The block process call uses block buffer mode */
1676 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1677 priv->features &= ~FEATURE_BLOCK_PROC;
1678
1679 err = pcim_enable_device(dev);
1680 if (err) {
1681 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1682 err);
1683 return err;
1684 }
1685 pcim_pin_device(dev);
1686
1687 /* Determine the address of the SMBus area */
1688 priv->smba = pci_resource_start(dev, SMBBAR);
1689 if (!priv->smba) {
1690 dev_err(&dev->dev,
1691 "SMBus base address uninitialized, upgrade BIOS\n");
1692 return -ENODEV;
1693 }
1694
1695 if (i801_acpi_probe(priv))
1696 return -ENODEV;
1697
1698 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1699 if (err) {
1700 dev_err(&dev->dev,
1701 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1702 priv->smba,
1703 (unsigned long long)pci_resource_end(dev, SMBBAR));
1704 i801_acpi_remove(priv);
1705 return err;
1706 }
1707
1708 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1709 i801_setup_hstcfg(priv);
1710 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1711 dev_info(&dev->dev, "Enabling SMBus device\n");
1712
1713 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1714 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1715 /* Disable SMBus interrupt feature if SMBus using SMI# */
1716 priv->features &= ~FEATURE_IRQ;
1717 }
1718 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1719 dev_info(&dev->dev, "SPD Write Disable is set\n");
1720
1721 /* Clear special mode bits */
1722 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1723 outb_p(inb_p(SMBAUXCTL(priv)) &
1724 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1725
1726 /* Default timeout in interrupt mode: 200 ms */
1727 priv->adapter.timeout = HZ / 5;
1728
1729 if (dev->irq == IRQ_NOTCONNECTED)
1730 priv->features &= ~FEATURE_IRQ;
1731
1732 if (priv->features & FEATURE_IRQ) {
1733 u16 pcists;
1734
1735 /* Complain if an interrupt is already pending */
1736 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1737 if (pcists & PCI_STATUS_INTERRUPT)
1738 dev_warn(&dev->dev, "An interrupt is pending!\n");
1739 }
1740
1741 if (priv->features & FEATURE_IRQ) {
1742 init_completion(&priv->done);
1743
1744 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1745 IRQF_SHARED, DRV_NAME, priv);
1746 if (err) {
1747 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1748 dev->irq, err);
1749 priv->features &= ~FEATURE_IRQ;
1750 }
1751 }
1752 dev_info(&dev->dev, "SMBus using %s\n",
1753 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1754
1755 /* Host notification uses an interrupt */
1756 if (!(priv->features & FEATURE_IRQ))
1757 priv->features &= ~FEATURE_HOST_NOTIFY;
1758
1759 /* Remember original Interrupt and Host Notify settings */
1760 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1761 if (priv->features & FEATURE_HOST_NOTIFY)
1762 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1763
1764 i801_add_tco(priv);
1765
1766 /*
1767 * adapter.name is used by platform code to find the main I801 adapter
1768 * to instantiante i2c_clients, do not change.
1769 */
1770 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1771 "SMBus %s adapter at %04lx",
1772 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1773 priv->smba);
1774
1775 err = i2c_add_adapter(&priv->adapter);
1776 if (err) {
1777 platform_device_unregister(priv->tco_pdev);
1778 i801_acpi_remove(priv);
1779 return err;
1780 }
1781
1782 i801_enable_host_notify(&priv->adapter);
1783
1784 i801_probe_optional_slaves(priv);
1785 /* We ignore errors - multiplexing is optional */
1786 i801_add_mux(priv);
1787
1788 pci_set_drvdata(dev, priv);
1789
1790 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1791 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1792 pm_runtime_use_autosuspend(&dev->dev);
1793 pm_runtime_put_autosuspend(&dev->dev);
1794 pm_runtime_allow(&dev->dev);
1795
1796 return 0;
1797 }
1798
i801_remove(struct pci_dev * dev)1799 static void i801_remove(struct pci_dev *dev)
1800 {
1801 struct i801_priv *priv = pci_get_drvdata(dev);
1802
1803 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1804 i801_disable_host_notify(priv);
1805 i801_del_mux(priv);
1806 i2c_del_adapter(&priv->adapter);
1807 i801_acpi_remove(priv);
1808 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1809
1810 platform_device_unregister(priv->tco_pdev);
1811
1812 /* if acpi_reserved is set then usage_count is incremented already */
1813 if (!priv->acpi_reserved)
1814 pm_runtime_get_noresume(&dev->dev);
1815
1816 /*
1817 * do not call pci_disable_device(dev) since it can cause hard hangs on
1818 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1819 */
1820 }
1821
i801_shutdown(struct pci_dev * dev)1822 static void i801_shutdown(struct pci_dev *dev)
1823 {
1824 struct i801_priv *priv = pci_get_drvdata(dev);
1825
1826 /* Restore config registers to avoid hard hang on some systems */
1827 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1828 i801_disable_host_notify(priv);
1829 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1830 }
1831
i801_suspend(struct device * dev)1832 static int i801_suspend(struct device *dev)
1833 {
1834 struct i801_priv *priv = dev_get_drvdata(dev);
1835
1836 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1837 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1838 return 0;
1839 }
1840
i801_resume(struct device * dev)1841 static int i801_resume(struct device *dev)
1842 {
1843 struct i801_priv *priv = dev_get_drvdata(dev);
1844
1845 i801_setup_hstcfg(priv);
1846 i801_enable_host_notify(&priv->adapter);
1847
1848 return 0;
1849 }
1850
1851 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1852
1853 static struct pci_driver i801_driver = {
1854 .name = DRV_NAME,
1855 .id_table = i801_ids,
1856 .probe = i801_probe,
1857 .remove = i801_remove,
1858 .shutdown = i801_shutdown,
1859 .driver = {
1860 .pm = pm_sleep_ptr(&i801_pm_ops),
1861 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1862 },
1863 };
1864
i2c_i801_init(void)1865 static int __init i2c_i801_init(void)
1866 {
1867 if (dmi_name_in_vendors("FUJITSU"))
1868 input_apanel_init();
1869 return pci_register_driver(&i801_driver);
1870 }
1871
i2c_i801_exit(void)1872 static void __exit i2c_i801_exit(void)
1873 {
1874 pci_unregister_driver(&i801_driver);
1875 }
1876
1877 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1878 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1879 MODULE_DESCRIPTION("I801 SMBus driver");
1880 MODULE_LICENSE("GPL");
1881
1882 module_init(i2c_i801_init);
1883 module_exit(i2c_i801_exit);
1884