1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * es8328.c -- ES8328 ALSA SoC Audio driver
4 *
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
6 *
7 * Author: Sean Cross <xobs@kosagi.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/of_device.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/regulator/consumer.h>
18 #include <sound/core.h>
19 #include <sound/initval.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include "es8328.h"
25
26 static const unsigned int rates_12288[] = {
27 8000, 12000, 16000, 24000, 32000, 48000, 96000,
28 };
29
30 static const int ratios_12288[] = {
31 10, 7, 6, 4, 3, 2, 0,
32 };
33
34 static const struct snd_pcm_hw_constraint_list constraints_12288 = {
35 .count = ARRAY_SIZE(rates_12288),
36 .list = rates_12288,
37 };
38
39 static const unsigned int rates_11289[] = {
40 8018, 11025, 22050, 44100, 88200,
41 };
42
43 static const int ratios_11289[] = {
44 9, 7, 4, 2, 0,
45 };
46
47 static const struct snd_pcm_hw_constraint_list constraints_11289 = {
48 .count = ARRAY_SIZE(rates_11289),
49 .list = rates_11289,
50 };
51
52 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
53 enum sgtl5000_regulator_supplies {
54 DVDD,
55 AVDD,
56 PVDD,
57 HPVDD,
58 ES8328_SUPPLY_NUM
59 };
60
61 /* vddd is optional supply */
62 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
63 "DVDD",
64 "AVDD",
65 "PVDD",
66 "HPVDD",
67 };
68
69 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
70 SNDRV_PCM_RATE_96000 | \
71 SNDRV_PCM_RATE_88200 | \
72 SNDRV_PCM_RATE_8000_48000)
73 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
74 SNDRV_PCM_FMTBIT_S18_3LE | \
75 SNDRV_PCM_FMTBIT_S20_3LE | \
76 SNDRV_PCM_FMTBIT_S24_LE | \
77 SNDRV_PCM_FMTBIT_S32_LE)
78
79 struct es8328_priv {
80 struct regmap *regmap;
81 struct clk *clk;
82 int playback_fs;
83 bool deemph;
84 int mclkdiv2;
85 const struct snd_pcm_hw_constraint_list *sysclk_constraints;
86 const int *mclk_ratios;
87 bool provider;
88 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
89 };
90
91 /*
92 * ES8328 Controls
93 */
94
95 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
96 "L + R Invert"};
97 static SOC_ENUM_SINGLE_DECL(adcpol,
98 ES8328_ADCCONTROL6, 6, adcpol_txt);
99
100 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
101 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
102 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
103 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
104
105 static const struct {
106 int rate;
107 unsigned int val;
108 } deemph_settings[] = {
109 { 0, ES8328_DACCONTROL6_DEEMPH_OFF },
110 { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
111 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
112 { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
113 };
114
es8328_set_deemph(struct snd_soc_component * component)115 static int es8328_set_deemph(struct snd_soc_component *component)
116 {
117 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
118 int val, i, best;
119
120 /*
121 * If we're using deemphasis select the nearest available sample
122 * rate.
123 */
124 if (es8328->deemph) {
125 best = 0;
126 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
127 if (abs(deemph_settings[i].rate - es8328->playback_fs) <
128 abs(deemph_settings[best].rate - es8328->playback_fs))
129 best = i;
130 }
131
132 val = deemph_settings[best].val;
133 } else {
134 val = ES8328_DACCONTROL6_DEEMPH_OFF;
135 }
136
137 dev_dbg(component->dev, "Set deemphasis %d\n", val);
138
139 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
140 ES8328_DACCONTROL6_DEEMPH_MASK, val);
141 }
142
es8328_get_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)143 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
144 struct snd_ctl_elem_value *ucontrol)
145 {
146 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
147 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
148
149 ucontrol->value.integer.value[0] = es8328->deemph;
150 return 0;
151 }
152
es8328_put_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)153 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
154 struct snd_ctl_elem_value *ucontrol)
155 {
156 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
157 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
158 unsigned int deemph = ucontrol->value.integer.value[0];
159 int ret;
160
161 if (deemph > 1)
162 return -EINVAL;
163
164 if (es8328->deemph == deemph)
165 return 0;
166
167 ret = es8328_set_deemph(component);
168 if (ret < 0)
169 return ret;
170
171 es8328->deemph = deemph;
172
173 return 1;
174 }
175
176
177
178 static const struct snd_kcontrol_new es8328_snd_controls[] = {
179 SOC_DOUBLE_R_TLV("Capture Digital Volume",
180 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
181 0, 0xc0, 1, dac_adc_tlv),
182 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
183
184 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
185 es8328_get_deemph, es8328_put_deemph),
186
187 SOC_ENUM("Capture Polarity", adcpol),
188
189 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
190 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
191 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
192 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
193 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
194 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
195 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
196 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
197
198 SOC_DOUBLE_R_TLV("PCM Volume",
199 ES8328_LDACVOL, ES8328_RDACVOL,
200 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
201
202 SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
203 ES8328_LOUT1VOL, ES8328_ROUT1VOL,
204 0, ES8328_OUT1VOL_MAX, 0, play_tlv),
205
206 SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
207 ES8328_LOUT2VOL, ES8328_ROUT2VOL,
208 0, ES8328_OUT2VOL_MAX, 0, play_tlv),
209
210 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
211 4, 0, 8, 0, mic_tlv),
212 };
213
214 /*
215 * DAPM Controls
216 */
217
218 static const char * const es8328_line_texts[] = {
219 "Line 1", "Line 2", "PGA", "Differential"};
220
221 static const struct soc_enum es8328_lline_enum =
222 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
223 ARRAY_SIZE(es8328_line_texts),
224 es8328_line_texts);
225 static const struct snd_kcontrol_new es8328_left_line_controls =
226 SOC_DAPM_ENUM("Route", es8328_lline_enum);
227
228 static const struct soc_enum es8328_rline_enum =
229 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
230 ARRAY_SIZE(es8328_line_texts),
231 es8328_line_texts);
232 static const struct snd_kcontrol_new es8328_right_line_controls =
233 SOC_DAPM_ENUM("Route", es8328_rline_enum);
234
235 /* Left Mixer */
236 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
237 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
238 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
239 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
240 };
241
242 /* Right Mixer */
243 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
244 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
245 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
246 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
247 };
248
249 static const char * const es8328_pga_sel[] = {
250 "Line 1", "Line 2", "Line 3", "Differential"};
251
252 /* Left PGA Mux */
253 static const struct soc_enum es8328_lpga_enum =
254 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
255 ARRAY_SIZE(es8328_pga_sel),
256 es8328_pga_sel);
257 static const struct snd_kcontrol_new es8328_left_pga_controls =
258 SOC_DAPM_ENUM("Route", es8328_lpga_enum);
259
260 /* Right PGA Mux */
261 static const struct soc_enum es8328_rpga_enum =
262 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
263 ARRAY_SIZE(es8328_pga_sel),
264 es8328_pga_sel);
265 static const struct snd_kcontrol_new es8328_right_pga_controls =
266 SOC_DAPM_ENUM("Route", es8328_rpga_enum);
267
268 /* Differential Mux */
269 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
270 static SOC_ENUM_SINGLE_DECL(diffmux,
271 ES8328_ADCCONTROL3, 7, es8328_diff_sel);
272 static const struct snd_kcontrol_new es8328_diffmux_controls =
273 SOC_DAPM_ENUM("Route", diffmux);
274
275 /* Mono ADC Mux */
276 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
277 "Mono (Right)", "Digital Mono"};
278 static SOC_ENUM_SINGLE_DECL(monomux,
279 ES8328_ADCCONTROL3, 3, es8328_mono_mux);
280 static const struct snd_kcontrol_new es8328_monomux_controls =
281 SOC_DAPM_ENUM("Route", monomux);
282
283 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
284 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
285 &es8328_diffmux_controls),
286 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
287 &es8328_monomux_controls),
288 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
289 &es8328_monomux_controls),
290
291 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
292 ES8328_ADCPOWER_AINL_OFF, 1,
293 &es8328_left_pga_controls),
294 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
295 ES8328_ADCPOWER_AINR_OFF, 1,
296 &es8328_right_pga_controls),
297
298 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
299 &es8328_left_line_controls),
300 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
301 &es8328_right_line_controls),
302
303 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
304 ES8328_ADCPOWER_ADCR_OFF, 1),
305 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
306 ES8328_ADCPOWER_ADCL_OFF, 1),
307
308 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
309 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
310 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
311 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
312
313 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
314 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
315 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
316 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
317
318 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
319 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
320 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
321 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
322
323 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
324 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
325 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
326 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
327
328 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
329 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
330 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
331 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
332
333 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
334 ES8328_DACPOWER_RDAC_OFF, 1),
335 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
336 ES8328_DACPOWER_LDAC_OFF, 1),
337
338 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0,
339 &es8328_left_mixer_controls[0],
340 ARRAY_SIZE(es8328_left_mixer_controls)),
341 SND_SOC_DAPM_MIXER("Right Mixer", ES8328_DACCONTROL20, 7, 0,
342 &es8328_right_mixer_controls[0],
343 ARRAY_SIZE(es8328_right_mixer_controls)),
344
345 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
346 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
347 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
348 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
349 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
350 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
351 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
352 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
353
354 SND_SOC_DAPM_OUTPUT("LOUT1"),
355 SND_SOC_DAPM_OUTPUT("ROUT1"),
356 SND_SOC_DAPM_OUTPUT("LOUT2"),
357 SND_SOC_DAPM_OUTPUT("ROUT2"),
358
359 SND_SOC_DAPM_INPUT("LINPUT1"),
360 SND_SOC_DAPM_INPUT("LINPUT2"),
361 SND_SOC_DAPM_INPUT("RINPUT1"),
362 SND_SOC_DAPM_INPUT("RINPUT2"),
363 };
364
365 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
366
367 { "Left Line Mux", "Line 1", "LINPUT1" },
368 { "Left Line Mux", "Line 2", "LINPUT2" },
369 { "Left Line Mux", "PGA", "Left PGA Mux" },
370 { "Left Line Mux", "Differential", "Differential Mux" },
371
372 { "Right Line Mux", "Line 1", "RINPUT1" },
373 { "Right Line Mux", "Line 2", "RINPUT2" },
374 { "Right Line Mux", "PGA", "Right PGA Mux" },
375 { "Right Line Mux", "Differential", "Differential Mux" },
376
377 { "Left PGA Mux", "Line 1", "LINPUT1" },
378 { "Left PGA Mux", "Line 2", "LINPUT2" },
379 { "Left PGA Mux", "Differential", "Differential Mux" },
380
381 { "Right PGA Mux", "Line 1", "RINPUT1" },
382 { "Right PGA Mux", "Line 2", "RINPUT2" },
383 { "Right PGA Mux", "Differential", "Differential Mux" },
384
385 { "Differential Mux", "Line 1", "LINPUT1" },
386 { "Differential Mux", "Line 1", "RINPUT1" },
387 { "Differential Mux", "Line 2", "LINPUT2" },
388 { "Differential Mux", "Line 2", "RINPUT2" },
389
390 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
391 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
392 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
393
394 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
395 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
396 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
397
398 { "Left ADC", NULL, "Left ADC Mux" },
399 { "Right ADC", NULL, "Right ADC Mux" },
400
401 { "ADC DIG", NULL, "ADC STM" },
402 { "ADC DIG", NULL, "ADC Vref" },
403 { "ADC DIG", NULL, "ADC DLL" },
404
405 { "Left ADC", NULL, "ADC DIG" },
406 { "Right ADC", NULL, "ADC DIG" },
407
408 { "Mic Bias", NULL, "Mic Bias Gen" },
409
410 { "Left Line Mux", "Line 1", "LINPUT1" },
411 { "Left Line Mux", "Line 2", "LINPUT2" },
412 { "Left Line Mux", "PGA", "Left PGA Mux" },
413 { "Left Line Mux", "Differential", "Differential Mux" },
414
415 { "Right Line Mux", "Line 1", "RINPUT1" },
416 { "Right Line Mux", "Line 2", "RINPUT2" },
417 { "Right Line Mux", "PGA", "Right PGA Mux" },
418 { "Right Line Mux", "Differential", "Differential Mux" },
419
420 { "Left Mixer", NULL, "Left DAC" },
421 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
422 { "Left Mixer", "Right Playback Switch", "Right DAC" },
423 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
424
425 { "Right Mixer", "Left Playback Switch", "Left DAC" },
426 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
427 { "Right Mixer", NULL, "Right DAC" },
428 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
429
430 { "DAC DIG", NULL, "DAC STM" },
431 { "DAC DIG", NULL, "DAC Vref" },
432 { "DAC DIG", NULL, "DAC DLL" },
433
434 { "Left DAC", NULL, "DAC DIG" },
435 { "Right DAC", NULL, "DAC DIG" },
436
437 { "Left Out 1", NULL, "Left Mixer" },
438 { "LOUT1", NULL, "Left Out 1" },
439 { "Right Out 1", NULL, "Right Mixer" },
440 { "ROUT1", NULL, "Right Out 1" },
441
442 { "Left Out 2", NULL, "Left Mixer" },
443 { "LOUT2", NULL, "Left Out 2" },
444 { "Right Out 2", NULL, "Right Mixer" },
445 { "ROUT2", NULL, "Right Out 2" },
446 };
447
es8328_mute(struct snd_soc_dai * dai,int mute,int direction)448 static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
449 {
450 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
451 ES8328_DACCONTROL3_DACMUTE,
452 mute ? ES8328_DACCONTROL3_DACMUTE : 0);
453 }
454
es8328_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)455 static int es8328_startup(struct snd_pcm_substream *substream,
456 struct snd_soc_dai *dai)
457 {
458 struct snd_soc_component *component = dai->component;
459 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
460
461 if (es8328->provider && es8328->sysclk_constraints)
462 snd_pcm_hw_constraint_list(substream->runtime, 0,
463 SNDRV_PCM_HW_PARAM_RATE,
464 es8328->sysclk_constraints);
465
466 return 0;
467 }
468
es8328_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)469 static int es8328_hw_params(struct snd_pcm_substream *substream,
470 struct snd_pcm_hw_params *params,
471 struct snd_soc_dai *dai)
472 {
473 struct snd_soc_component *component = dai->component;
474 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
475 int i;
476 int reg;
477 int wl;
478 int ratio;
479
480 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
481 reg = ES8328_DACCONTROL2;
482 else
483 reg = ES8328_ADCCONTROL5;
484
485 if (es8328->provider) {
486 if (!es8328->sysclk_constraints) {
487 dev_err(component->dev, "No MCLK configured\n");
488 return -EINVAL;
489 }
490
491 for (i = 0; i < es8328->sysclk_constraints->count; i++)
492 if (es8328->sysclk_constraints->list[i] ==
493 params_rate(params))
494 break;
495
496 if (i == es8328->sysclk_constraints->count) {
497 dev_err(component->dev,
498 "LRCLK %d unsupported with current clock\n",
499 params_rate(params));
500 return -EINVAL;
501 }
502 ratio = es8328->mclk_ratios[i];
503 } else {
504 ratio = 0;
505 es8328->mclkdiv2 = 0;
506 }
507
508 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
509 ES8328_MASTERMODE_MCLKDIV2,
510 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
511
512 switch (params_width(params)) {
513 case 16:
514 wl = 3;
515 break;
516 case 18:
517 wl = 2;
518 break;
519 case 20:
520 wl = 1;
521 break;
522 case 24:
523 wl = 0;
524 break;
525 case 32:
526 wl = 4;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
533 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
534 ES8328_DACCONTROL1_DACWL_MASK,
535 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
536
537 es8328->playback_fs = params_rate(params);
538 es8328_set_deemph(component);
539 } else
540 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
541 ES8328_ADCCONTROL4_ADCWL_MASK,
542 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
543
544 return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
545 }
546
es8328_set_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)547 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
548 int clk_id, unsigned int freq, int dir)
549 {
550 struct snd_soc_component *component = codec_dai->component;
551 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
552 int mclkdiv2 = 0;
553
554 switch (freq) {
555 case 0:
556 es8328->sysclk_constraints = NULL;
557 es8328->mclk_ratios = NULL;
558 break;
559 case 22579200:
560 mclkdiv2 = 1;
561 fallthrough;
562 case 11289600:
563 es8328->sysclk_constraints = &constraints_11289;
564 es8328->mclk_ratios = ratios_11289;
565 break;
566 case 24576000:
567 mclkdiv2 = 1;
568 fallthrough;
569 case 12288000:
570 es8328->sysclk_constraints = &constraints_12288;
571 es8328->mclk_ratios = ratios_12288;
572 break;
573 default:
574 return -EINVAL;
575 }
576
577 es8328->mclkdiv2 = mclkdiv2;
578 return 0;
579 }
580
es8328_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)581 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
582 unsigned int fmt)
583 {
584 struct snd_soc_component *component = codec_dai->component;
585 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
586 u8 dac_mode = 0;
587 u8 adc_mode = 0;
588
589 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
590 case SND_SOC_DAIFMT_CBP_CFP:
591 /* Master serial port mode, with BCLK generated automatically */
592 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
593 ES8328_MASTERMODE_MSC,
594 ES8328_MASTERMODE_MSC);
595 es8328->provider = true;
596 break;
597 case SND_SOC_DAIFMT_CBC_CFC:
598 /* Slave serial port mode */
599 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
600 ES8328_MASTERMODE_MSC, 0);
601 es8328->provider = false;
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 /* interface format */
608 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
609 case SND_SOC_DAIFMT_I2S:
610 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
611 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
612 break;
613 case SND_SOC_DAIFMT_RIGHT_J:
614 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
615 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
616 break;
617 case SND_SOC_DAIFMT_LEFT_J:
618 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
619 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
620 break;
621 default:
622 return -EINVAL;
623 }
624
625 /* clock inversion */
626 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
627 return -EINVAL;
628
629 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
630 ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
631 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
632 ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
633
634 return 0;
635 }
636
es8328_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)637 static int es8328_set_bias_level(struct snd_soc_component *component,
638 enum snd_soc_bias_level level)
639 {
640 switch (level) {
641 case SND_SOC_BIAS_ON:
642 break;
643
644 case SND_SOC_BIAS_PREPARE:
645 /* VREF, VMID=2x50k, digital enabled */
646 snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
647 snd_soc_component_update_bits(component, ES8328_CONTROL1,
648 ES8328_CONTROL1_VMIDSEL_MASK |
649 ES8328_CONTROL1_ENREF,
650 ES8328_CONTROL1_VMIDSEL_50k |
651 ES8328_CONTROL1_ENREF);
652 break;
653
654 case SND_SOC_BIAS_STANDBY:
655 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
656 snd_soc_component_update_bits(component, ES8328_CONTROL1,
657 ES8328_CONTROL1_VMIDSEL_MASK |
658 ES8328_CONTROL1_ENREF,
659 ES8328_CONTROL1_VMIDSEL_5k |
660 ES8328_CONTROL1_ENREF);
661
662 /* Charge caps */
663 msleep(100);
664 }
665
666 snd_soc_component_write(component, ES8328_CONTROL2,
667 ES8328_CONTROL2_OVERCURRENT_ON |
668 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
669
670 /* VREF, VMID=2*500k, digital stopped */
671 snd_soc_component_update_bits(component, ES8328_CONTROL1,
672 ES8328_CONTROL1_VMIDSEL_MASK |
673 ES8328_CONTROL1_ENREF,
674 ES8328_CONTROL1_VMIDSEL_500k |
675 ES8328_CONTROL1_ENREF);
676 break;
677
678 case SND_SOC_BIAS_OFF:
679 snd_soc_component_update_bits(component, ES8328_CONTROL1,
680 ES8328_CONTROL1_VMIDSEL_MASK |
681 ES8328_CONTROL1_ENREF,
682 0);
683 break;
684 }
685 return 0;
686 }
687
688 static const struct snd_soc_dai_ops es8328_dai_ops = {
689 .startup = es8328_startup,
690 .hw_params = es8328_hw_params,
691 .mute_stream = es8328_mute,
692 .set_sysclk = es8328_set_sysclk,
693 .set_fmt = es8328_set_dai_fmt,
694 .no_capture_mute = 1,
695 };
696
697 static struct snd_soc_dai_driver es8328_dai = {
698 .name = "es8328-hifi-analog",
699 .playback = {
700 .stream_name = "Playback",
701 .channels_min = 2,
702 .channels_max = 2,
703 .rates = ES8328_RATES,
704 .formats = ES8328_FORMATS,
705 },
706 .capture = {
707 .stream_name = "Capture",
708 .channels_min = 2,
709 .channels_max = 2,
710 .rates = ES8328_RATES,
711 .formats = ES8328_FORMATS,
712 },
713 .ops = &es8328_dai_ops,
714 .symmetric_rate = 1,
715 };
716
es8328_suspend(struct snd_soc_component * component)717 static int es8328_suspend(struct snd_soc_component *component)
718 {
719 struct es8328_priv *es8328;
720 int ret;
721
722 es8328 = snd_soc_component_get_drvdata(component);
723
724 clk_disable_unprepare(es8328->clk);
725
726 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
727 es8328->supplies);
728 if (ret) {
729 dev_err(component->dev, "unable to disable regulators\n");
730 return ret;
731 }
732 return 0;
733 }
734
es8328_resume(struct snd_soc_component * component)735 static int es8328_resume(struct snd_soc_component *component)
736 {
737 struct regmap *regmap = dev_get_regmap(component->dev, NULL);
738 struct es8328_priv *es8328;
739 int ret;
740
741 es8328 = snd_soc_component_get_drvdata(component);
742
743 ret = clk_prepare_enable(es8328->clk);
744 if (ret) {
745 dev_err(component->dev, "unable to enable clock\n");
746 return ret;
747 }
748
749 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
750 es8328->supplies);
751 if (ret) {
752 dev_err(component->dev, "unable to enable regulators\n");
753 return ret;
754 }
755
756 regcache_mark_dirty(regmap);
757 ret = regcache_sync(regmap);
758 if (ret) {
759 dev_err(component->dev, "unable to sync regcache\n");
760 return ret;
761 }
762
763 return 0;
764 }
765
es8328_component_probe(struct snd_soc_component * component)766 static int es8328_component_probe(struct snd_soc_component *component)
767 {
768 struct es8328_priv *es8328;
769 int ret;
770
771 es8328 = snd_soc_component_get_drvdata(component);
772
773 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
774 es8328->supplies);
775 if (ret) {
776 dev_err(component->dev, "unable to enable regulators\n");
777 return ret;
778 }
779
780 /* Setup clocks */
781 es8328->clk = devm_clk_get(component->dev, NULL);
782 if (IS_ERR(es8328->clk)) {
783 dev_err(component->dev, "codec clock missing or invalid\n");
784 ret = PTR_ERR(es8328->clk);
785 goto clk_fail;
786 }
787
788 ret = clk_prepare_enable(es8328->clk);
789 if (ret) {
790 dev_err(component->dev, "unable to prepare codec clk\n");
791 goto clk_fail;
792 }
793
794 return 0;
795
796 clk_fail:
797 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
798 es8328->supplies);
799 return ret;
800 }
801
es8328_remove(struct snd_soc_component * component)802 static void es8328_remove(struct snd_soc_component *component)
803 {
804 struct es8328_priv *es8328;
805
806 es8328 = snd_soc_component_get_drvdata(component);
807
808 clk_disable_unprepare(es8328->clk);
809
810 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
811 es8328->supplies);
812 }
813
814 const struct regmap_config es8328_regmap_config = {
815 .reg_bits = 8,
816 .val_bits = 8,
817 .max_register = ES8328_REG_MAX,
818 .cache_type = REGCACHE_MAPLE,
819 .use_single_read = true,
820 .use_single_write = true,
821 };
822 EXPORT_SYMBOL_GPL(es8328_regmap_config);
823
824 static const struct snd_soc_component_driver es8328_component_driver = {
825 .probe = es8328_component_probe,
826 .remove = es8328_remove,
827 .suspend = es8328_suspend,
828 .resume = es8328_resume,
829 .set_bias_level = es8328_set_bias_level,
830 .controls = es8328_snd_controls,
831 .num_controls = ARRAY_SIZE(es8328_snd_controls),
832 .dapm_widgets = es8328_dapm_widgets,
833 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
834 .dapm_routes = es8328_dapm_routes,
835 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
836 .suspend_bias_off = 1,
837 .idle_bias_on = 1,
838 .use_pmdown_time = 1,
839 .endianness = 1,
840 };
841
es8328_probe(struct device * dev,struct regmap * regmap)842 int es8328_probe(struct device *dev, struct regmap *regmap)
843 {
844 struct es8328_priv *es8328;
845 int ret;
846 int i;
847
848 if (IS_ERR(regmap))
849 return PTR_ERR(regmap);
850
851 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
852 if (es8328 == NULL)
853 return -ENOMEM;
854
855 es8328->regmap = regmap;
856
857 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
858 es8328->supplies[i].supply = supply_names[i];
859
860 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
861 es8328->supplies);
862 if (ret) {
863 dev_err(dev, "unable to get regulators\n");
864 return ret;
865 }
866
867 dev_set_drvdata(dev, es8328);
868
869 return devm_snd_soc_register_component(dev,
870 &es8328_component_driver, &es8328_dai, 1);
871 }
872 EXPORT_SYMBOL_GPL(es8328_probe);
873
874 MODULE_DESCRIPTION("ASoC ES8328 driver");
875 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
876 MODULE_LICENSE("GPL");
877