1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <asm/io.h>
9 #include <asm/arch/ddr.h>
10 #include <power/pmic.h>
11 #include <power/stpmu1.h>
12
13 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)14 void board_debug_uart_init(void)
15 {
16 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
17
18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
19 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
20
21 /* UART4 clock enable */
22 setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
23
24 #define GPIOG_BASE 0x50008000
25 /* GPIOG clock enable */
26 writel(BIT(6), RCC_MP_AHB4ENSETR);
27 /* GPIO configuration for EVAL board
28 * => Uart4 TX = G11
29 */
30 writel(0xffbfffff, GPIOG_BASE + 0x00);
31 writel(0x00006000, GPIOG_BASE + 0x24);
32 #else
33
34 #error("CONFIG_DEBUG_UART_BASE: not supported value")
35
36 #endif
37 }
38 #endif
39
40 #ifdef CONFIG_PMIC_STPMU1
board_ddr_power_init(void)41 int board_ddr_power_init(void)
42 {
43 struct udevice *dev;
44 int ret;
45
46 ret = uclass_get_device_by_driver(UCLASS_PMIC,
47 DM_GET_DRIVER(pmic_stpmu1), &dev);
48 if (ret)
49 /* No PMIC on board */
50 return 0;
51
52 /* Set LDO3 to sync mode */
53 ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
54 if (ret < 0)
55 return ret;
56
57 ret &= ~STPMU1_LDO3_MODE;
58 ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
59 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
60
61 ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
62 ret);
63 if (ret < 0)
64 return ret;
65
66 /* Set BUCK2 to 1.35V */
67 ret = pmic_clrsetbits(dev,
68 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
69 STPMU1_BUCK_OUTPUT_MASK,
70 STPMU1_BUCK2_1350000V);
71 if (ret < 0)
72 return ret;
73
74 /* Enable BUCK2 and VREF */
75 ret = pmic_clrsetbits(dev,
76 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
77 STPMU1_BUCK_EN, STPMU1_BUCK_EN);
78 if (ret < 0)
79 return ret;
80
81 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
82
83 ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
84 STPMU1_VREF_EN, STPMU1_VREF_EN);
85 if (ret < 0)
86 return ret;
87
88 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
89
90 /* Enable LDO3 */
91 ret = pmic_clrsetbits(dev,
92 STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
93 STPMU1_LDO_EN, STPMU1_LDO_EN);
94 if (ret < 0)
95 return ret;
96
97 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
98
99 return 0;
100 }
101 #endif
102