1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #ifndef __RSWITCH_H__ 8 #define __RSWITCH_H__ 9 10 #include <linux/platform_device.h> 11 #include "rcar_gen4_ptp.h" 12 13 #define RSWITCH_MAX_NUM_QUEUES 128 14 15 #define RSWITCH_NUM_PORTS 3 16 #define rswitch_for_each_enabled_port(priv, i) \ 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 18 if (priv->rdev[i]->disabled) \ 19 continue; \ 20 else 21 22 #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \ 23 for (i--; i >= 0; i--) \ 24 if (priv->rdev[i]->disabled) \ 25 continue; \ 26 else 27 28 #define TX_RING_SIZE 1024 29 #define RX_RING_SIZE 1024 30 #define TS_RING_SIZE (TX_RING_SIZE * RSWITCH_NUM_PORTS) 31 32 #define RSWITCH_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 33 #define RSWITCH_DESC_BUF_SIZE 2048 34 #define RSWITCH_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 35 #define RSWITCH_ALIGN 128 36 #define RSWITCH_BUF_SIZE (RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \ 37 RSWITCH_TAILROOM + RSWITCH_ALIGN) 38 #define RSWITCH_MAP_BUF_SIZE (RSWITCH_BUF_SIZE - RSWITCH_HEADROOM) 39 #define RSWITCH_MAX_CTAG_PCP 7 40 41 #define RSWITCH_TIMEOUT_US 100000 42 43 #define RSWITCH_TOP_OFFSET 0x00008000 44 #define RSWITCH_COMA_OFFSET 0x00009000 45 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 46 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 47 #define RSWITCH_GWCA0_OFFSET 0x00010000 48 #define RSWITCH_GWCA1_OFFSET 0x00012000 49 50 /* TODO: hardcoded ETHA/GWCA settings for now */ 51 #define GWCA_IRQ_RESOURCE_NAME "gwca0_rxtx%d" 52 #define GWCA_IRQ_NAME "rswitch: gwca0_rxtx%d" 53 #define GWCA_NUM_IRQS 8 54 #define GWCA_INDEX 0 55 #define AGENT_INDEX_GWCA 3 56 #define GWCA_IPV_NUM 0 57 #define GWRO RSWITCH_GWCA0_OFFSET 58 59 #define GWCA_TS_IRQ_RESOURCE_NAME "gwca0_rxts0" 60 #define GWCA_TS_IRQ_NAME "rswitch: gwca0_rxts0" 61 #define GWCA_TS_IRQ_BIT BIT(0) 62 63 #define FWRO 0 64 #define TPRO RSWITCH_TOP_OFFSET 65 #define CARO RSWITCH_COMA_OFFSET 66 #define TARO 0 67 #define RMRO 0x1000 68 enum rswitch_reg { 69 FWGC = FWRO + 0x0000, 70 FWTTC0 = FWRO + 0x0010, 71 FWTTC1 = FWRO + 0x0014, 72 FWLBMC = FWRO + 0x0018, 73 FWCEPTC = FWRO + 0x0020, 74 FWCEPRC0 = FWRO + 0x0024, 75 FWCEPRC1 = FWRO + 0x0028, 76 FWCEPRC2 = FWRO + 0x002c, 77 FWCLPTC = FWRO + 0x0030, 78 FWCLPRC = FWRO + 0x0034, 79 FWCMPTC = FWRO + 0x0040, 80 FWEMPTC = FWRO + 0x0044, 81 FWSDMPTC = FWRO + 0x0050, 82 FWSDMPVC = FWRO + 0x0054, 83 FWLBWMC0 = FWRO + 0x0080, 84 FWPC00 = FWRO + 0x0100, 85 FWPC10 = FWRO + 0x0104, 86 FWPC20 = FWRO + 0x0108, 87 FWCTGC00 = FWRO + 0x0400, 88 FWCTGC10 = FWRO + 0x0404, 89 FWCTTC00 = FWRO + 0x0408, 90 FWCTTC10 = FWRO + 0x040c, 91 FWCTTC200 = FWRO + 0x0410, 92 FWCTSC00 = FWRO + 0x0420, 93 FWCTSC10 = FWRO + 0x0424, 94 FWCTSC20 = FWRO + 0x0428, 95 FWCTSC30 = FWRO + 0x042c, 96 FWCTSC40 = FWRO + 0x0430, 97 FWTWBFC0 = FWRO + 0x1000, 98 FWTWBFVC0 = FWRO + 0x1004, 99 FWTHBFC0 = FWRO + 0x1400, 100 FWTHBFV0C0 = FWRO + 0x1404, 101 FWTHBFV1C0 = FWRO + 0x1408, 102 FWFOBFC0 = FWRO + 0x1800, 103 FWFOBFV0C0 = FWRO + 0x1804, 104 FWFOBFV1C0 = FWRO + 0x1808, 105 FWRFC0 = FWRO + 0x1c00, 106 FWRFVC0 = FWRO + 0x1c04, 107 FWCFC0 = FWRO + 0x2000, 108 FWCFMC00 = FWRO + 0x2004, 109 FWIP4SC = FWRO + 0x4008, 110 FWIP6SC = FWRO + 0x4018, 111 FWIP6OC = FWRO + 0x401c, 112 FWL2SC = FWRO + 0x4020, 113 FWSFHEC = FWRO + 0x4030, 114 FWSHCR0 = FWRO + 0x4040, 115 FWSHCR1 = FWRO + 0x4044, 116 FWSHCR2 = FWRO + 0x4048, 117 FWSHCR3 = FWRO + 0x404c, 118 FWSHCR4 = FWRO + 0x4050, 119 FWSHCR5 = FWRO + 0x4054, 120 FWSHCR6 = FWRO + 0x4058, 121 FWSHCR7 = FWRO + 0x405c, 122 FWSHCR8 = FWRO + 0x4060, 123 FWSHCR9 = FWRO + 0x4064, 124 FWSHCR10 = FWRO + 0x4068, 125 FWSHCR11 = FWRO + 0x406c, 126 FWSHCR12 = FWRO + 0x4070, 127 FWSHCR13 = FWRO + 0x4074, 128 FWSHCRR = FWRO + 0x4078, 129 FWLTHHEC = FWRO + 0x4090, 130 FWLTHHC = FWRO + 0x4094, 131 FWLTHTL0 = FWRO + 0x40a0, 132 FWLTHTL1 = FWRO + 0x40a4, 133 FWLTHTL2 = FWRO + 0x40a8, 134 FWLTHTL3 = FWRO + 0x40ac, 135 FWLTHTL4 = FWRO + 0x40b0, 136 FWLTHTL5 = FWRO + 0x40b4, 137 FWLTHTL6 = FWRO + 0x40b8, 138 FWLTHTL7 = FWRO + 0x40bc, 139 FWLTHTL80 = FWRO + 0x40c0, 140 FWLTHTL9 = FWRO + 0x40d0, 141 FWLTHTLR = FWRO + 0x40d4, 142 FWLTHTIM = FWRO + 0x40e0, 143 FWLTHTEM = FWRO + 0x40e4, 144 FWLTHTS0 = FWRO + 0x4100, 145 FWLTHTS1 = FWRO + 0x4104, 146 FWLTHTS2 = FWRO + 0x4108, 147 FWLTHTS3 = FWRO + 0x410c, 148 FWLTHTS4 = FWRO + 0x4110, 149 FWLTHTSR0 = FWRO + 0x4120, 150 FWLTHTSR1 = FWRO + 0x4124, 151 FWLTHTSR2 = FWRO + 0x4128, 152 FWLTHTSR3 = FWRO + 0x412c, 153 FWLTHTSR40 = FWRO + 0x4130, 154 FWLTHTSR5 = FWRO + 0x4140, 155 FWLTHTR = FWRO + 0x4150, 156 FWLTHTRR0 = FWRO + 0x4154, 157 FWLTHTRR1 = FWRO + 0x4158, 158 FWLTHTRR2 = FWRO + 0x415c, 159 FWLTHTRR3 = FWRO + 0x4160, 160 FWLTHTRR4 = FWRO + 0x4164, 161 FWLTHTRR5 = FWRO + 0x4168, 162 FWLTHTRR6 = FWRO + 0x416c, 163 FWLTHTRR7 = FWRO + 0x4170, 164 FWLTHTRR8 = FWRO + 0x4174, 165 FWLTHTRR9 = FWRO + 0x4180, 166 FWLTHTRR10 = FWRO + 0x4190, 167 FWIPHEC = FWRO + 0x4214, 168 FWIPHC = FWRO + 0x4218, 169 FWIPTL0 = FWRO + 0x4220, 170 FWIPTL1 = FWRO + 0x4224, 171 FWIPTL2 = FWRO + 0x4228, 172 FWIPTL3 = FWRO + 0x422c, 173 FWIPTL4 = FWRO + 0x4230, 174 FWIPTL5 = FWRO + 0x4234, 175 FWIPTL6 = FWRO + 0x4238, 176 FWIPTL7 = FWRO + 0x4240, 177 FWIPTL8 = FWRO + 0x4250, 178 FWIPTLR = FWRO + 0x4254, 179 FWIPTIM = FWRO + 0x4260, 180 FWIPTEM = FWRO + 0x4264, 181 FWIPTS0 = FWRO + 0x4270, 182 FWIPTS1 = FWRO + 0x4274, 183 FWIPTS2 = FWRO + 0x4278, 184 FWIPTS3 = FWRO + 0x427c, 185 FWIPTS4 = FWRO + 0x4280, 186 FWIPTSR0 = FWRO + 0x4284, 187 FWIPTSR1 = FWRO + 0x4288, 188 FWIPTSR2 = FWRO + 0x428c, 189 FWIPTSR3 = FWRO + 0x4290, 190 FWIPTSR4 = FWRO + 0x42a0, 191 FWIPTR = FWRO + 0x42b0, 192 FWIPTRR0 = FWRO + 0x42b4, 193 FWIPTRR1 = FWRO + 0x42b8, 194 FWIPTRR2 = FWRO + 0x42bc, 195 FWIPTRR3 = FWRO + 0x42c0, 196 FWIPTRR4 = FWRO + 0x42c4, 197 FWIPTRR5 = FWRO + 0x42c8, 198 FWIPTRR6 = FWRO + 0x42cc, 199 FWIPTRR7 = FWRO + 0x42d0, 200 FWIPTRR8 = FWRO + 0x42e0, 201 FWIPTRR9 = FWRO + 0x42f0, 202 FWIPHLEC = FWRO + 0x4300, 203 FWIPAGUSPC = FWRO + 0x4500, 204 FWIPAGC = FWRO + 0x4504, 205 FWIPAGM0 = FWRO + 0x4510, 206 FWIPAGM1 = FWRO + 0x4514, 207 FWIPAGM2 = FWRO + 0x4518, 208 FWIPAGM3 = FWRO + 0x451c, 209 FWIPAGM4 = FWRO + 0x4520, 210 FWMACHEC = FWRO + 0x4620, 211 FWMACHC = FWRO + 0x4624, 212 FWMACTL0 = FWRO + 0x4630, 213 FWMACTL1 = FWRO + 0x4634, 214 FWMACTL2 = FWRO + 0x4638, 215 FWMACTL3 = FWRO + 0x463c, 216 FWMACTL4 = FWRO + 0x4640, 217 FWMACTL5 = FWRO + 0x4650, 218 FWMACTLR = FWRO + 0x4654, 219 FWMACTIM = FWRO + 0x4660, 220 FWMACTEM = FWRO + 0x4664, 221 FWMACTS0 = FWRO + 0x4670, 222 FWMACTS1 = FWRO + 0x4674, 223 FWMACTSR0 = FWRO + 0x4678, 224 FWMACTSR1 = FWRO + 0x467c, 225 FWMACTSR2 = FWRO + 0x4680, 226 FWMACTSR3 = FWRO + 0x4690, 227 FWMACTR = FWRO + 0x46a0, 228 FWMACTRR0 = FWRO + 0x46a4, 229 FWMACTRR1 = FWRO + 0x46a8, 230 FWMACTRR2 = FWRO + 0x46ac, 231 FWMACTRR3 = FWRO + 0x46b0, 232 FWMACTRR4 = FWRO + 0x46b4, 233 FWMACTRR5 = FWRO + 0x46c0, 234 FWMACTRR6 = FWRO + 0x46d0, 235 FWMACHLEC = FWRO + 0x4700, 236 FWMACAGUSPC = FWRO + 0x4880, 237 FWMACAGC = FWRO + 0x4884, 238 FWMACAGM0 = FWRO + 0x4888, 239 FWMACAGM1 = FWRO + 0x488c, 240 FWVLANTEC = FWRO + 0x4900, 241 FWVLANTL0 = FWRO + 0x4910, 242 FWVLANTL1 = FWRO + 0x4914, 243 FWVLANTL2 = FWRO + 0x4918, 244 FWVLANTL3 = FWRO + 0x4920, 245 FWVLANTL4 = FWRO + 0x4930, 246 FWVLANTLR = FWRO + 0x4934, 247 FWVLANTIM = FWRO + 0x4940, 248 FWVLANTEM = FWRO + 0x4944, 249 FWVLANTS = FWRO + 0x4950, 250 FWVLANTSR0 = FWRO + 0x4954, 251 FWVLANTSR1 = FWRO + 0x4958, 252 FWVLANTSR2 = FWRO + 0x4960, 253 FWVLANTSR3 = FWRO + 0x4970, 254 FWPBFC0 = FWRO + 0x4a00, 255 FWPBFCSDC00 = FWRO + 0x4a04, 256 FWL23URL0 = FWRO + 0x4e00, 257 FWL23URL1 = FWRO + 0x4e04, 258 FWL23URL2 = FWRO + 0x4e08, 259 FWL23URL3 = FWRO + 0x4e0c, 260 FWL23URLR = FWRO + 0x4e10, 261 FWL23UTIM = FWRO + 0x4e20, 262 FWL23URR = FWRO + 0x4e30, 263 FWL23URRR0 = FWRO + 0x4e34, 264 FWL23URRR1 = FWRO + 0x4e38, 265 FWL23URRR2 = FWRO + 0x4e3c, 266 FWL23URRR3 = FWRO + 0x4e40, 267 FWL23URMC0 = FWRO + 0x4f00, 268 FWPMFGC0 = FWRO + 0x5000, 269 FWPGFC0 = FWRO + 0x5100, 270 FWPGFIGSC0 = FWRO + 0x5104, 271 FWPGFENC0 = FWRO + 0x5108, 272 FWPGFENM0 = FWRO + 0x510c, 273 FWPGFCSTC00 = FWRO + 0x5110, 274 FWPGFCSTC10 = FWRO + 0x5114, 275 FWPGFCSTM00 = FWRO + 0x5118, 276 FWPGFCSTM10 = FWRO + 0x511c, 277 FWPGFCTC0 = FWRO + 0x5120, 278 FWPGFCTM0 = FWRO + 0x5124, 279 FWPGFHCC0 = FWRO + 0x5128, 280 FWPGFSM0 = FWRO + 0x512c, 281 FWPGFGC0 = FWRO + 0x5130, 282 FWPGFGL0 = FWRO + 0x5500, 283 FWPGFGL1 = FWRO + 0x5504, 284 FWPGFGLR = FWRO + 0x5518, 285 FWPGFGR = FWRO + 0x5510, 286 FWPGFGRR0 = FWRO + 0x5514, 287 FWPGFGRR1 = FWRO + 0x5518, 288 FWPGFRIM = FWRO + 0x5520, 289 FWPMTRFC0 = FWRO + 0x5600, 290 FWPMTRCBSC0 = FWRO + 0x5604, 291 FWPMTRC0RC0 = FWRO + 0x5608, 292 FWPMTREBSC0 = FWRO + 0x560c, 293 FWPMTREIRC0 = FWRO + 0x5610, 294 FWPMTRFM0 = FWRO + 0x5614, 295 FWFTL0 = FWRO + 0x6000, 296 FWFTL1 = FWRO + 0x6004, 297 FWFTLR = FWRO + 0x6008, 298 FWFTOC = FWRO + 0x6010, 299 FWFTOPC = FWRO + 0x6014, 300 FWFTIM = FWRO + 0x6020, 301 FWFTR = FWRO + 0x6030, 302 FWFTRR0 = FWRO + 0x6034, 303 FWFTRR1 = FWRO + 0x6038, 304 FWFTRR2 = FWRO + 0x603c, 305 FWSEQNGC0 = FWRO + 0x6100, 306 FWSEQNGM0 = FWRO + 0x6104, 307 FWSEQNRC = FWRO + 0x6200, 308 FWCTFDCN0 = FWRO + 0x6300, 309 FWLTHFDCN0 = FWRO + 0x6304, 310 FWIPFDCN0 = FWRO + 0x6308, 311 FWLTWFDCN0 = FWRO + 0x630c, 312 FWPBFDCN0 = FWRO + 0x6310, 313 FWMHLCN0 = FWRO + 0x6314, 314 FWIHLCN0 = FWRO + 0x6318, 315 FWICRDCN0 = FWRO + 0x6500, 316 FWWMRDCN0 = FWRO + 0x6504, 317 FWCTRDCN0 = FWRO + 0x6508, 318 FWLTHRDCN0 = FWRO + 0x650c, 319 FWIPRDCN0 = FWRO + 0x6510, 320 FWLTWRDCN0 = FWRO + 0x6514, 321 FWPBRDCN0 = FWRO + 0x6518, 322 FWPMFDCN0 = FWRO + 0x6700, 323 FWPGFDCN0 = FWRO + 0x6780, 324 FWPMGDCN0 = FWRO + 0x6800, 325 FWPMYDCN0 = FWRO + 0x6804, 326 FWPMRDCN0 = FWRO + 0x6808, 327 FWFRPPCN0 = FWRO + 0x6a00, 328 FWFRDPCN0 = FWRO + 0x6a04, 329 FWEIS00 = FWRO + 0x7900, 330 FWEIE00 = FWRO + 0x7904, 331 FWEID00 = FWRO + 0x7908, 332 FWEIS1 = FWRO + 0x7a00, 333 FWEIE1 = FWRO + 0x7a04, 334 FWEID1 = FWRO + 0x7a08, 335 FWEIS2 = FWRO + 0x7a10, 336 FWEIE2 = FWRO + 0x7a14, 337 FWEID2 = FWRO + 0x7a18, 338 FWEIS3 = FWRO + 0x7a20, 339 FWEIE3 = FWRO + 0x7a24, 340 FWEID3 = FWRO + 0x7a28, 341 FWEIS4 = FWRO + 0x7a30, 342 FWEIE4 = FWRO + 0x7a34, 343 FWEID4 = FWRO + 0x7a38, 344 FWEIS5 = FWRO + 0x7a40, 345 FWEIE5 = FWRO + 0x7a44, 346 FWEID5 = FWRO + 0x7a48, 347 FWEIS60 = FWRO + 0x7a50, 348 FWEIE60 = FWRO + 0x7a54, 349 FWEID60 = FWRO + 0x7a58, 350 FWEIS61 = FWRO + 0x7a60, 351 FWEIE61 = FWRO + 0x7a64, 352 FWEID61 = FWRO + 0x7a68, 353 FWEIS62 = FWRO + 0x7a70, 354 FWEIE62 = FWRO + 0x7a74, 355 FWEID62 = FWRO + 0x7a78, 356 FWEIS63 = FWRO + 0x7a80, 357 FWEIE63 = FWRO + 0x7a84, 358 FWEID63 = FWRO + 0x7a88, 359 FWEIS70 = FWRO + 0x7a90, 360 FWEIE70 = FWRO + 0x7A94, 361 FWEID70 = FWRO + 0x7a98, 362 FWEIS71 = FWRO + 0x7aa0, 363 FWEIE71 = FWRO + 0x7aa4, 364 FWEID71 = FWRO + 0x7aa8, 365 FWEIS72 = FWRO + 0x7ab0, 366 FWEIE72 = FWRO + 0x7ab4, 367 FWEID72 = FWRO + 0x7ab8, 368 FWEIS73 = FWRO + 0x7ac0, 369 FWEIE73 = FWRO + 0x7ac4, 370 FWEID73 = FWRO + 0x7ac8, 371 FWEIS80 = FWRO + 0x7ad0, 372 FWEIE80 = FWRO + 0x7ad4, 373 FWEID80 = FWRO + 0x7ad8, 374 FWEIS81 = FWRO + 0x7ae0, 375 FWEIE81 = FWRO + 0x7ae4, 376 FWEID81 = FWRO + 0x7ae8, 377 FWEIS82 = FWRO + 0x7af0, 378 FWEIE82 = FWRO + 0x7af4, 379 FWEID82 = FWRO + 0x7af8, 380 FWEIS83 = FWRO + 0x7b00, 381 FWEIE83 = FWRO + 0x7b04, 382 FWEID83 = FWRO + 0x7b08, 383 FWMIS0 = FWRO + 0x7c00, 384 FWMIE0 = FWRO + 0x7c04, 385 FWMID0 = FWRO + 0x7c08, 386 FWSCR0 = FWRO + 0x7d00, 387 FWSCR1 = FWRO + 0x7d04, 388 FWSCR2 = FWRO + 0x7d08, 389 FWSCR3 = FWRO + 0x7d0c, 390 FWSCR4 = FWRO + 0x7d10, 391 FWSCR5 = FWRO + 0x7d14, 392 FWSCR6 = FWRO + 0x7d18, 393 FWSCR7 = FWRO + 0x7d1c, 394 FWSCR8 = FWRO + 0x7d20, 395 FWSCR9 = FWRO + 0x7d24, 396 FWSCR10 = FWRO + 0x7d28, 397 FWSCR11 = FWRO + 0x7d2c, 398 FWSCR12 = FWRO + 0x7d30, 399 FWSCR13 = FWRO + 0x7d34, 400 FWSCR14 = FWRO + 0x7d38, 401 FWSCR15 = FWRO + 0x7d3c, 402 FWSCR16 = FWRO + 0x7d40, 403 FWSCR17 = FWRO + 0x7d44, 404 FWSCR18 = FWRO + 0x7d48, 405 FWSCR19 = FWRO + 0x7d4c, 406 FWSCR20 = FWRO + 0x7d50, 407 FWSCR21 = FWRO + 0x7d54, 408 FWSCR22 = FWRO + 0x7d58, 409 FWSCR23 = FWRO + 0x7d5c, 410 FWSCR24 = FWRO + 0x7d60, 411 FWSCR25 = FWRO + 0x7d64, 412 FWSCR26 = FWRO + 0x7d68, 413 FWSCR27 = FWRO + 0x7d6c, 414 FWSCR28 = FWRO + 0x7d70, 415 FWSCR29 = FWRO + 0x7d74, 416 FWSCR30 = FWRO + 0x7d78, 417 FWSCR31 = FWRO + 0x7d7c, 418 FWSCR32 = FWRO + 0x7d80, 419 FWSCR33 = FWRO + 0x7d84, 420 FWSCR34 = FWRO + 0x7d88, 421 FWSCR35 = FWRO + 0x7d8c, 422 FWSCR36 = FWRO + 0x7d90, 423 FWSCR37 = FWRO + 0x7d94, 424 FWSCR38 = FWRO + 0x7d98, 425 FWSCR39 = FWRO + 0x7d9c, 426 FWSCR40 = FWRO + 0x7da0, 427 FWSCR41 = FWRO + 0x7da4, 428 FWSCR42 = FWRO + 0x7da8, 429 FWSCR43 = FWRO + 0x7dac, 430 FWSCR44 = FWRO + 0x7db0, 431 FWSCR45 = FWRO + 0x7db4, 432 FWSCR46 = FWRO + 0x7db8, 433 434 TPEMIMC0 = TPRO + 0x0000, 435 TPEMIMC1 = TPRO + 0x0004, 436 TPEMIMC2 = TPRO + 0x0008, 437 TPEMIMC3 = TPRO + 0x000c, 438 TPEMIMC4 = TPRO + 0x0010, 439 TPEMIMC5 = TPRO + 0x0014, 440 TPEMIMC60 = TPRO + 0x0080, 441 TPEMIMC70 = TPRO + 0x0100, 442 TSIM = TPRO + 0x0700, 443 TFIM = TPRO + 0x0704, 444 TCIM = TPRO + 0x0708, 445 TGIM0 = TPRO + 0x0710, 446 TGIM1 = TPRO + 0x0714, 447 TEIM0 = TPRO + 0x0720, 448 TEIM1 = TPRO + 0x0724, 449 TEIM2 = TPRO + 0x0728, 450 451 RIPV = CARO + 0x0000, 452 RRC = CARO + 0x0004, 453 RCEC = CARO + 0x0008, 454 RCDC = CARO + 0x000c, 455 RSSIS = CARO + 0x0010, 456 RSSIE = CARO + 0x0014, 457 RSSID = CARO + 0x0018, 458 CABPIBWMC = CARO + 0x0020, 459 CABPWMLC = CARO + 0x0040, 460 CABPPFLC0 = CARO + 0x0050, 461 CABPPWMLC0 = CARO + 0x0060, 462 CABPPPFLC00 = CARO + 0x00a0, 463 CABPULC = CARO + 0x0100, 464 CABPIRM = CARO + 0x0140, 465 CABPPCM = CARO + 0x0144, 466 CABPLCM = CARO + 0x0148, 467 CABPCPM = CARO + 0x0180, 468 CABPMCPM = CARO + 0x0200, 469 CARDNM = CARO + 0x0280, 470 CARDMNM = CARO + 0x0284, 471 CARDCN = CARO + 0x0290, 472 CAEIS0 = CARO + 0x0300, 473 CAEIE0 = CARO + 0x0304, 474 CAEID0 = CARO + 0x0308, 475 CAEIS1 = CARO + 0x0310, 476 CAEIE1 = CARO + 0x0314, 477 CAEID1 = CARO + 0x0318, 478 CAMIS0 = CARO + 0x0340, 479 CAMIE0 = CARO + 0x0344, 480 CAMID0 = CARO + 0x0348, 481 CAMIS1 = CARO + 0x0350, 482 CAMIE1 = CARO + 0x0354, 483 CAMID1 = CARO + 0x0358, 484 CASCR = CARO + 0x0380, 485 486 EAMC = TARO + 0x0000, 487 EAMS = TARO + 0x0004, 488 EAIRC = TARO + 0x0010, 489 EATDQSC = TARO + 0x0014, 490 EATDQC = TARO + 0x0018, 491 EATDQAC = TARO + 0x001c, 492 EATPEC = TARO + 0x0020, 493 EATMFSC0 = TARO + 0x0040, 494 EATDQDC0 = TARO + 0x0060, 495 EATDQM0 = TARO + 0x0080, 496 EATDQMLM0 = TARO + 0x00a0, 497 EACTQC = TARO + 0x0100, 498 EACTDQDC = TARO + 0x0104, 499 EACTDQM = TARO + 0x0108, 500 EACTDQMLM = TARO + 0x010c, 501 EAVCC = TARO + 0x0130, 502 EAVTC = TARO + 0x0134, 503 EATTFC = TARO + 0x0138, 504 EACAEC = TARO + 0x0200, 505 EACC = TARO + 0x0204, 506 EACAIVC0 = TARO + 0x0220, 507 EACAULC0 = TARO + 0x0240, 508 EACOEM = TARO + 0x0260, 509 EACOIVM0 = TARO + 0x0280, 510 EACOULM0 = TARO + 0x02a0, 511 EACGSM = TARO + 0x02c0, 512 EATASC = TARO + 0x0300, 513 EATASENC0 = TARO + 0x0320, 514 EATASCTENC = TARO + 0x0340, 515 EATASENM0 = TARO + 0x0360, 516 EATASCTENM = TARO + 0x0380, 517 EATASCSTC0 = TARO + 0x03a0, 518 EATASCSTC1 = TARO + 0x03a4, 519 EATASCSTM0 = TARO + 0x03a8, 520 EATASCSTM1 = TARO + 0x03ac, 521 EATASCTC = TARO + 0x03b0, 522 EATASCTM = TARO + 0x03b4, 523 EATASGL0 = TARO + 0x03c0, 524 EATASGL1 = TARO + 0x03c4, 525 EATASGLR = TARO + 0x03c8, 526 EATASGR = TARO + 0x03d0, 527 EATASGRR = TARO + 0x03d4, 528 EATASHCC = TARO + 0x03e0, 529 EATASRIRM = TARO + 0x03e4, 530 EATASSM = TARO + 0x03e8, 531 EAUSMFSECN = TARO + 0x0400, 532 EATFECN = TARO + 0x0404, 533 EAFSECN = TARO + 0x0408, 534 EADQOECN = TARO + 0x040c, 535 EADQSECN = TARO + 0x0410, 536 EACKSECN = TARO + 0x0414, 537 EAEIS0 = TARO + 0x0500, 538 EAEIE0 = TARO + 0x0504, 539 EAEID0 = TARO + 0x0508, 540 EAEIS1 = TARO + 0x0510, 541 EAEIE1 = TARO + 0x0514, 542 EAEID1 = TARO + 0x0518, 543 EAEIS2 = TARO + 0x0520, 544 EAEIE2 = TARO + 0x0524, 545 EAEID2 = TARO + 0x0528, 546 EASCR = TARO + 0x0580, 547 548 MPSM = RMRO + 0x0000, 549 MPIC = RMRO + 0x0004, 550 MPIM = RMRO + 0x0008, 551 MIOC = RMRO + 0x0010, 552 MIOM = RMRO + 0x0014, 553 MXMS = RMRO + 0x0018, 554 MTFFC = RMRO + 0x0020, 555 MTPFC = RMRO + 0x0024, 556 MTPFC2 = RMRO + 0x0028, 557 MTPFC30 = RMRO + 0x0030, 558 MTATC0 = RMRO + 0x0050, 559 MTIM = RMRO + 0x0060, 560 MRGC = RMRO + 0x0080, 561 MRMAC0 = RMRO + 0x0084, 562 MRMAC1 = RMRO + 0x0088, 563 MRAFC = RMRO + 0x008c, 564 MRSCE = RMRO + 0x0090, 565 MRSCP = RMRO + 0x0094, 566 MRSCC = RMRO + 0x0098, 567 MRFSCE = RMRO + 0x009c, 568 MRFSCP = RMRO + 0x00a0, 569 MTRC = RMRO + 0x00a4, 570 MRIM = RMRO + 0x00a8, 571 MRPFM = RMRO + 0x00ac, 572 MPFC0 = RMRO + 0x0100, 573 MLVC = RMRO + 0x0180, 574 MEEEC = RMRO + 0x0184, 575 MLBC = RMRO + 0x0188, 576 MXGMIIC = RMRO + 0x0190, 577 MPCH = RMRO + 0x0194, 578 MANC = RMRO + 0x0198, 579 MANM = RMRO + 0x019c, 580 MPLCA1 = RMRO + 0x01a0, 581 MPLCA2 = RMRO + 0x01a4, 582 MPLCA3 = RMRO + 0x01a8, 583 MPLCA4 = RMRO + 0x01ac, 584 MPLCAM = RMRO + 0x01b0, 585 MHDC1 = RMRO + 0x01c0, 586 MHDC2 = RMRO + 0x01c4, 587 MEIS = RMRO + 0x0200, 588 MEIE = RMRO + 0x0204, 589 MEID = RMRO + 0x0208, 590 MMIS0 = RMRO + 0x0210, 591 MMIE0 = RMRO + 0x0214, 592 MMID0 = RMRO + 0x0218, 593 MMIS1 = RMRO + 0x0220, 594 MMIE1 = RMRO + 0x0224, 595 MMID1 = RMRO + 0x0228, 596 MMIS2 = RMRO + 0x0230, 597 MMIE2 = RMRO + 0x0234, 598 MMID2 = RMRO + 0x0238, 599 MMPFTCT = RMRO + 0x0300, 600 MAPFTCT = RMRO + 0x0304, 601 MPFRCT = RMRO + 0x0308, 602 MFCICT = RMRO + 0x030c, 603 MEEECT = RMRO + 0x0310, 604 MMPCFTCT0 = RMRO + 0x0320, 605 MAPCFTCT0 = RMRO + 0x0330, 606 MPCFRCT0 = RMRO + 0x0340, 607 MHDCC = RMRO + 0x0350, 608 MROVFC = RMRO + 0x0354, 609 MRHCRCEC = RMRO + 0x0358, 610 MRXBCE = RMRO + 0x0400, 611 MRXBCP = RMRO + 0x0404, 612 MRGFCE = RMRO + 0x0408, 613 MRGFCP = RMRO + 0x040c, 614 MRBFC = RMRO + 0x0410, 615 MRMFC = RMRO + 0x0414, 616 MRUFC = RMRO + 0x0418, 617 MRPEFC = RMRO + 0x041c, 618 MRNEFC = RMRO + 0x0420, 619 MRFMEFC = RMRO + 0x0424, 620 MRFFMEFC = RMRO + 0x0428, 621 MRCFCEFC = RMRO + 0x042c, 622 MRFCEFC = RMRO + 0x0430, 623 MRRCFEFC = RMRO + 0x0434, 624 MRUEFC = RMRO + 0x043c, 625 MROEFC = RMRO + 0x0440, 626 MRBOEC = RMRO + 0x0444, 627 MTXBCE = RMRO + 0x0500, 628 MTXBCP = RMRO + 0x0504, 629 MTGFCE = RMRO + 0x0508, 630 MTGFCP = RMRO + 0x050c, 631 MTBFC = RMRO + 0x0510, 632 MTMFC = RMRO + 0x0514, 633 MTUFC = RMRO + 0x0518, 634 MTEFC = RMRO + 0x051c, 635 636 GWMC = GWRO + 0x0000, 637 GWMS = GWRO + 0x0004, 638 GWIRC = GWRO + 0x0010, 639 GWRDQSC = GWRO + 0x0014, 640 GWRDQC = GWRO + 0x0018, 641 GWRDQAC = GWRO + 0x001c, 642 GWRGC = GWRO + 0x0020, 643 GWRMFSC0 = GWRO + 0x0040, 644 GWRDQDC0 = GWRO + 0x0060, 645 GWRDQM0 = GWRO + 0x0080, 646 GWRDQMLM0 = GWRO + 0x00a0, 647 GWMTIRM = GWRO + 0x0100, 648 GWMSTLS = GWRO + 0x0104, 649 GWMSTLR = GWRO + 0x0108, 650 GWMSTSS = GWRO + 0x010c, 651 GWMSTSR = GWRO + 0x0110, 652 GWMAC0 = GWRO + 0x0120, 653 GWMAC1 = GWRO + 0x0124, 654 GWVCC = GWRO + 0x0130, 655 GWVTC = GWRO + 0x0134, 656 GWTTFC = GWRO + 0x0138, 657 GWTDCAC00 = GWRO + 0x0140, 658 GWTDCAC10 = GWRO + 0x0144, 659 GWTSDCC0 = GWRO + 0x0160, 660 GWTNM = GWRO + 0x0180, 661 GWTMNM = GWRO + 0x0184, 662 GWAC = GWRO + 0x0190, 663 GWDCBAC0 = GWRO + 0x0194, 664 GWDCBAC1 = GWRO + 0x0198, 665 GWIICBSC = GWRO + 0x019c, 666 GWMDNC = GWRO + 0x01a0, 667 GWTRC0 = GWRO + 0x0200, 668 GWTPC0 = GWRO + 0x0300, 669 GWARIRM = GWRO + 0x0380, 670 GWDCC0 = GWRO + 0x0400, 671 GWAARSS = GWRO + 0x0800, 672 GWAARSR0 = GWRO + 0x0804, 673 GWAARSR1 = GWRO + 0x0808, 674 GWIDAUAS0 = GWRO + 0x0840, 675 GWIDASM0 = GWRO + 0x0880, 676 GWIDASAM00 = GWRO + 0x0900, 677 GWIDASAM10 = GWRO + 0x0904, 678 GWIDACAM00 = GWRO + 0x0980, 679 GWIDACAM10 = GWRO + 0x0984, 680 GWGRLC = GWRO + 0x0a00, 681 GWGRLULC = GWRO + 0x0a04, 682 GWRLIVC0 = GWRO + 0x0a80, 683 GWRLULC0 = GWRO + 0x0a84, 684 GWIDPC = GWRO + 0x0b00, 685 GWIDC0 = GWRO + 0x0c00, 686 GWDIS0 = GWRO + 0x1100, 687 GWDIE0 = GWRO + 0x1104, 688 GWDID0 = GWRO + 0x1108, 689 GWTSDIS = GWRO + 0x1180, 690 GWTSDIE = GWRO + 0x1184, 691 GWTSDID = GWRO + 0x1188, 692 GWEIS0 = GWRO + 0x1190, 693 GWEIE0 = GWRO + 0x1194, 694 GWEID0 = GWRO + 0x1198, 695 GWEIS1 = GWRO + 0x11a0, 696 GWEIE1 = GWRO + 0x11a4, 697 GWEID1 = GWRO + 0x11a8, 698 GWEIS20 = GWRO + 0x1200, 699 GWEIE20 = GWRO + 0x1204, 700 GWEID20 = GWRO + 0x1208, 701 GWEIS3 = GWRO + 0x1280, 702 GWEIE3 = GWRO + 0x1284, 703 GWEID3 = GWRO + 0x1288, 704 GWEIS4 = GWRO + 0x1290, 705 GWEIE4 = GWRO + 0x1294, 706 GWEID4 = GWRO + 0x1298, 707 GWEIS5 = GWRO + 0x12a0, 708 GWEIE5 = GWRO + 0x12a4, 709 GWEID5 = GWRO + 0x12a8, 710 GWSCR0 = GWRO + 0x1800, 711 GWSCR1 = GWRO + 0x1900, 712 }; 713 714 /* ETHA/RMAC */ 715 enum rswitch_etha_mode { 716 EAMC_OPC_RESET, 717 EAMC_OPC_DISABLE, 718 EAMC_OPC_CONFIG, 719 EAMC_OPC_OPERATION, 720 }; 721 722 #define EAMS_OPS_MASK EAMC_OPC_OPERATION 723 724 #define EAVCC_VEM_SC_TAG (0x3 << 16) 725 726 #define MPIC_PIS GENMASK(2, 0) 727 #define MPIC_PIS_GMII 2 728 #define MPIC_PIS_XGMII 4 729 #define MPIC_LSC GENMASK(5, 3) 730 #define MPIC_LSC_100M 1 731 #define MPIC_LSC_1G 2 732 #define MPIC_LSC_2_5G 3 733 734 #define MDIO_READ_C45 0x03 735 #define MDIO_WRITE_C45 0x01 736 737 #define MPSM_PSME BIT(0) 738 #define MPSM_MFF_C45 BIT(2) 739 #define MPSM_PRD_SHIFT 16 740 #define MPSM_PRD_MASK GENMASK(31, MPSM_PRD_SHIFT) 741 742 /* Completion flags */ 743 #define MMIS1_PAACS BIT(2) /* Address */ 744 #define MMIS1_PWACS BIT(1) /* Write */ 745 #define MMIS1_PRACS BIT(0) /* Read */ 746 #define MMIS1_CLEAR_FLAGS 0xf 747 748 #define MPIC_PSMCS_SHIFT 16 749 #define MPIC_PSMCS_MASK GENMASK(22, MPIC_PSMCS_SHIFT) 750 #define MPIC_PSMCS(val) ((val) << MPIC_PSMCS_SHIFT) 751 752 #define MPIC_PSMHT_SHIFT 24 753 #define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT) 754 #define MPIC_PSMHT(val) ((val) << MPIC_PSMHT_SHIFT) 755 756 #define MLVC_PLV BIT(16) 757 758 /* GWCA */ 759 enum rswitch_gwca_mode { 760 GWMC_OPC_RESET, 761 GWMC_OPC_DISABLE, 762 GWMC_OPC_CONFIG, 763 GWMC_OPC_OPERATION, 764 }; 765 766 #define GWMS_OPS_MASK GWMC_OPC_OPERATION 767 768 #define GWMTIRM_MTIOG BIT(0) 769 #define GWMTIRM_MTR BIT(1) 770 771 #define GWVCC_VEM_SC_TAG (0x3 << 16) 772 773 #define GWARIRM_ARIOG BIT(0) 774 #define GWARIRM_ARR BIT(1) 775 776 #define GWDCC_BALR BIT(24) 777 #define GWDCC_DCP_MASK GENMASK(18, 16) 778 #define GWDCC_DCP(prio) FIELD_PREP(GWDCC_DCP_MASK, (prio)) 779 #define GWDCC_DQT BIT(11) 780 #define GWDCC_ETS BIT(9) 781 #define GWDCC_EDE BIT(8) 782 783 #define GWTRC(queue) (GWTRC0 + (queue) / 32 * 4) 784 #define GWTPC_PPPL(ipv) BIT(ipv) 785 #define GWDCC_OFFS(queue) (GWDCC0 + (queue) * 4) 786 787 #define GWDIS(i) (GWDIS0 + (i) * 0x10) 788 #define GWDIE(i) (GWDIE0 + (i) * 0x10) 789 #define GWDID(i) (GWDID0 + (i) * 0x10) 790 791 /* COMA */ 792 #define RRC_RR BIT(0) 793 #define RRC_RR_CLR 0 794 #define RCEC_ACE_DEFAULT (BIT(0) | BIT(AGENT_INDEX_GWCA)) 795 #define RCEC_RCE BIT(16) 796 #define RCDC_RCD BIT(16) 797 798 #define CABPIRM_BPIOG BIT(0) 799 #define CABPIRM_BPR BIT(1) 800 801 #define CABPPFLC_INIT_VALUE 0x00800080 802 803 /* MFWD */ 804 #define FWPC0_LTHTA BIT(0) 805 #define FWPC0_IP4UE BIT(3) 806 #define FWPC0_IP4TE BIT(4) 807 #define FWPC0_IP4OE BIT(5) 808 #define FWPC0_L2SE BIT(9) 809 #define FWPC0_IP4EA BIT(10) 810 #define FWPC0_IPDSA BIT(12) 811 #define FWPC0_IPHLA BIT(18) 812 #define FWPC0_MACSDA BIT(20) 813 #define FWPC0_MACHLA BIT(26) 814 #define FWPC0_MACHMA BIT(27) 815 #define FWPC0_VLANSA BIT(28) 816 817 #define FWPC0(i) (FWPC00 + (i) * 0x10) 818 #define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ 819 FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ 820 FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ 821 FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) 822 #define FWPC1(i) (FWPC10 + (i) * 0x10) 823 #define FWPC1_DDE BIT(0) 824 825 #define FWPBFC(i) (FWPBFC0 + (i) * 0x10) 826 827 #define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04) 828 829 /* TOP */ 830 #define TPEMIMC7(queue) (TPEMIMC70 + (queue) * 4) 831 832 /* Descriptors */ 833 enum RX_DS_CC_BIT { 834 RX_DS = 0x0fff, /* Data size */ 835 RX_TR = 0x1000, /* Truncation indication */ 836 RX_EI = 0x2000, /* Error indication */ 837 RX_PS = 0xc000, /* Padding selection */ 838 }; 839 840 enum TX_DS_TAGL_BIT { 841 TX_DS = 0x0fff, /* Data size */ 842 TX_TAGL = 0xf000, /* Frame tag LSBs */ 843 }; 844 845 enum DIE_DT { 846 /* Frame data */ 847 DT_FSINGLE = 0x80, 848 DT_FSTART = 0x90, 849 DT_FMID = 0xa0, 850 DT_FEND = 0xb0, 851 852 /* Chain control */ 853 DT_LEMPTY = 0xc0, 854 DT_EEMPTY = 0xd0, 855 DT_LINKFIX = 0x00, 856 DT_LINK = 0xe0, 857 DT_EOS = 0xf0, 858 /* HW/SW arbitration */ 859 DT_FEMPTY = 0x40, 860 DT_FEMPTY_IS = 0x10, 861 DT_FEMPTY_IC = 0x20, 862 DT_FEMPTY_ND = 0x30, 863 DT_FEMPTY_START = 0x50, 864 DT_FEMPTY_MID = 0x60, 865 DT_FEMPTY_END = 0x70, 866 867 DT_MASK = 0xf0, 868 DIE = 0x08, /* Descriptor Interrupt Enable */ 869 }; 870 871 /* Both transmission and reception */ 872 #define INFO1_FMT BIT(2) 873 #define INFO1_TXC BIT(3) 874 875 /* For transmission */ 876 #define INFO1_TSUN(val) ((u64)(val) << 8ULL) 877 #define INFO1_IPV(prio) ((u64)(prio) << 28ULL) 878 #define INFO1_CSD0(index) ((u64)(index) << 32ULL) 879 #define INFO1_CSD1(index) ((u64)(index) << 40ULL) 880 #define INFO1_DV(port_vector) ((u64)(port_vector) << 48ULL) 881 882 /* For reception */ 883 #define INFO1_SPN(port) ((u64)(port) << 36ULL) 884 885 /* For timestamp descriptor in dptrl (Byte 4 to 7) */ 886 #define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0)) 887 #define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8) 888 #define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16) 889 #define TS_DESC_TN(dptrl) ((dptrl) & BIT(24)) 890 891 struct rswitch_desc { 892 __le16 info_ds; /* Descriptor size */ 893 u8 die_dt; /* Descriptor interrupt enable and type */ 894 __u8 dptrh; /* Descriptor pointer MSB */ 895 __le32 dptrl; /* Descriptor pointer LSW */ 896 } __packed; 897 898 struct rswitch_ts_desc { 899 struct rswitch_desc desc; 900 __le32 ts_nsec; 901 __le32 ts_sec; 902 } __packed; 903 904 struct rswitch_ext_desc { 905 struct rswitch_desc desc; 906 __le64 info1; 907 } __packed; 908 909 struct rswitch_ext_ts_desc { 910 struct rswitch_desc desc; 911 __le64 info1; 912 __le32 ts_nsec; 913 __le32 ts_sec; 914 } __packed; 915 916 struct rswitch_etha { 917 unsigned int index; 918 void __iomem *addr; 919 void __iomem *coma_addr; 920 bool external_phy; 921 struct mii_bus *mii; 922 phy_interface_t phy_interface; 923 u32 psmcs; 924 u8 mac_addr[MAX_ADDR_LEN]; 925 int link; 926 int speed; 927 928 /* This hardware could not be initialized twice so that marked 929 * this flag to avoid multiple initialization. 930 */ 931 bool operated; 932 }; 933 934 /* The datasheet said descriptor "chain" and/or "queue". For consistency of 935 * name, this driver calls "queue". 936 */ 937 struct rswitch_gwca_queue { 938 union { 939 struct rswitch_ext_desc *tx_ring; 940 struct rswitch_ext_ts_desc *rx_ring; 941 struct rswitch_ts_desc *ts_ring; 942 }; 943 944 /* Common */ 945 dma_addr_t ring_dma; 946 unsigned int ring_size; 947 unsigned int cur; 948 unsigned int dirty; 949 950 /* For [rt]x_ring */ 951 unsigned int index; 952 bool dir_tx; 953 struct net_device *ndev; /* queue to ndev for irq */ 954 955 union { 956 /* For TX */ 957 struct { 958 struct sk_buff **skbs; 959 dma_addr_t *unmap_addrs; 960 }; 961 /* For RX */ 962 struct { 963 void **rx_bufs; 964 }; 965 }; 966 }; 967 968 #define RSWITCH_NUM_IRQ_REGS (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32)) 969 struct rswitch_gwca { 970 unsigned int index; 971 struct rswitch_desc *linkfix_table; 972 dma_addr_t linkfix_table_dma; 973 u32 linkfix_table_size; 974 struct rswitch_gwca_queue *queues; 975 int num_queues; 976 struct rswitch_gwca_queue ts_queue; 977 DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES); 978 u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS]; 979 u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS]; 980 int speed; 981 }; 982 983 #define NUM_QUEUES_PER_NDEV 2 984 #define TS_TAGS_PER_PORT 256 985 struct rswitch_device { 986 struct rswitch_private *priv; 987 struct net_device *ndev; 988 struct napi_struct napi; 989 void __iomem *addr; 990 struct rswitch_gwca_queue *tx_queue; 991 struct rswitch_gwca_queue *rx_queue; 992 struct sk_buff *ts_skb[TS_TAGS_PER_PORT]; 993 DECLARE_BITMAP(ts_skb_used, TS_TAGS_PER_PORT); 994 bool disabled; 995 996 int port; 997 struct rswitch_etha *etha; 998 struct device_node *np_port; 999 struct phy *serdes; 1000 }; 1001 1002 struct rswitch_mfwd_mac_table_entry { 1003 int queue_index; 1004 unsigned char addr[MAX_ADDR_LEN]; 1005 }; 1006 1007 struct rswitch_mfwd { 1008 struct rswitch_mac_table_entry *mac_table_entries; 1009 int num_mac_table_entries; 1010 }; 1011 1012 struct rswitch_private { 1013 struct platform_device *pdev; 1014 void __iomem *addr; 1015 struct rcar_gen4_ptp_private *ptp_priv; 1016 1017 struct rswitch_device *rdev[RSWITCH_NUM_PORTS]; 1018 DECLARE_BITMAP(opened_ports, RSWITCH_NUM_PORTS); 1019 1020 struct rswitch_gwca gwca; 1021 struct rswitch_etha etha[RSWITCH_NUM_PORTS]; 1022 struct rswitch_mfwd mfwd; 1023 1024 spinlock_t lock; /* lock interrupt registers' control */ 1025 struct clk *clk; 1026 1027 bool etha_no_runtime_change; 1028 bool gwca_halt; 1029 }; 1030 1031 #endif /* #ifndef __RSWITCH_H__ */ 1032