1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <asm/mach-imx/spi.h>
19 #include <asm/io.h>
20 #include <linux/sizes.h>
21 #include <common.h>
22 #include <fsl_esdhc.h>
23 #include <i2c.h>
24 #include <mmc.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
34 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
41 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
42 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43
44 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46
47 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
49 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
50 PAD_CTL_SRE_FAST)
51
52 #define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
53
dram_init(void)54 int dram_init(void)
55 {
56 gd->ram_size = imx_ddr_size();
57
58 return 0;
59 }
60
61 static iomux_v3_cfg_t const uart1_pads[] = {
62 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
63 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
64 };
65
66 #ifdef CONFIG_SPL_BUILD
67 static iomux_v3_cfg_t const usdhc1_pads[] = {
68 /* 8 bit SD */
69 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79
80 /*CD pin*/
81 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
82 };
83
84 static iomux_v3_cfg_t const usdhc2_pads[] = {
85 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91
92 /*CD pin*/
93 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
94 };
95
96 static iomux_v3_cfg_t const usdhc3_pads[] = {
97 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103
104 /*CD pin*/
105 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 };
107 #endif
108
109 static iomux_v3_cfg_t const fec_pads[] = {
110 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
120 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
121 };
122
123 #ifdef CONFIG_MXC_SPI
124 static iomux_v3_cfg_t ecspi1_pads[] = {
125 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
126 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
127 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
128 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 };
130
board_spi_cs_gpio(unsigned bus,unsigned cs)131 int board_spi_cs_gpio(unsigned bus, unsigned cs)
132 {
133 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
134 }
135
setup_spi(void)136 static void setup_spi(void)
137 {
138 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
139 }
140 #endif
141
setup_iomux_uart(void)142 static void setup_iomux_uart(void)
143 {
144 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
145 }
146
setup_iomux_fec(void)147 static void setup_iomux_fec(void)
148 {
149 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
150
151 /* Power up LAN8720 PHY */
152 gpio_request(ETH_PHY_POWER, "eth_pwr");
153 gpio_direction_output(ETH_PHY_POWER , 1);
154 udelay(15000);
155 }
156
board_mmc_get_env_dev(int devno)157 int board_mmc_get_env_dev(int devno)
158 {
159 return devno;
160 }
161
162 #ifdef CONFIG_DM_PMIC_PFUZE100
power_init_board(void)163 int power_init_board(void)
164 {
165 struct udevice *dev;
166 int ret;
167 u32 dev_id, rev_id, i;
168 u32 switch_num = 6;
169 u32 offset = PFUZE100_SW1CMODE;
170
171 ret = pmic_get("pfuze100", &dev);
172 if (ret == -ENODEV)
173 return 0;
174
175 if (ret != 0)
176 return ret;
177
178 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
179 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
180 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
181
182 /* set SW1AB staby volatage 0.975V */
183 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
184
185 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
186 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
187
188 /* set SW1C staby volatage 0.975V */
189 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
190
191 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
192 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
193
194 /* Init mode to APS_PFM */
195 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
196
197 for (i = 0; i < switch_num - 1; i++)
198 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
199
200 return 0;
201 }
202 #endif
203
204 #ifdef CONFIG_FEC_MXC
board_eth_init(bd_t * bis)205 int board_eth_init(bd_t *bis)
206 {
207 setup_iomux_fec();
208
209 return cpu_eth_init(bis);
210 }
211
setup_fec(void)212 static int setup_fec(void)
213 {
214 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
215
216 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
217 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
218
219 return enable_fec_anatop_clock(0, ENET_50MHZ);
220 }
221 #endif
222
board_early_init_f(void)223 int board_early_init_f(void)
224 {
225 setup_iomux_uart();
226
227 return 0;
228 }
229
board_init(void)230 int board_init(void)
231 {
232 /* address of boot parameters */
233 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
234
235 #ifdef CONFIG_MXC_SPI
236 gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
237 setup_spi();
238 #endif
239
240 #ifdef CONFIG_FEC_MXC
241 setup_fec();
242 #endif
243
244 return 0;
245 }
246
checkboard(void)247 int checkboard(void)
248 {
249 puts("Board: MX6SLEVK\n");
250
251 return 0;
252 }
253
254 #ifdef CONFIG_SPL_BUILD
255 #include <spl.h>
256 #include <linux/libfdt.h>
257
258 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
259 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
260 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
261
262 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
263 {USDHC1_BASE_ADDR},
264 {USDHC2_BASE_ADDR, 0, 4},
265 {USDHC3_BASE_ADDR, 0, 4},
266 };
267
board_mmc_getcd(struct mmc * mmc)268 int board_mmc_getcd(struct mmc *mmc)
269 {
270 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
271 int ret = 0;
272
273 switch (cfg->esdhc_base) {
274 case USDHC1_BASE_ADDR:
275 gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
276 ret = !gpio_get_value(USDHC1_CD_GPIO);
277 break;
278 case USDHC2_BASE_ADDR:
279 gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
280 ret = !gpio_get_value(USDHC2_CD_GPIO);
281 break;
282 case USDHC3_BASE_ADDR:
283 gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
284 ret = !gpio_get_value(USDHC3_CD_GPIO);
285 break;
286 }
287
288 return ret;
289 }
290
board_mmc_init(bd_t * bis)291 int board_mmc_init(bd_t *bis)
292 {
293 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
294 u32 val;
295 u32 port;
296
297 val = readl(&src_regs->sbmr1);
298
299 /* Boot from USDHC */
300 port = (val >> 11) & 0x3;
301 switch (port) {
302 case 0:
303 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
304 ARRAY_SIZE(usdhc1_pads));
305 gpio_direction_input(USDHC1_CD_GPIO);
306 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
308 break;
309 case 1:
310 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
311 ARRAY_SIZE(usdhc2_pads));
312 gpio_direction_input(USDHC2_CD_GPIO);
313 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
314 usdhc_cfg[0].max_bus_width = 4;
315 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
316 break;
317 case 2:
318 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
319 ARRAY_SIZE(usdhc3_pads));
320 gpio_direction_input(USDHC3_CD_GPIO);
321 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
322 usdhc_cfg[0].max_bus_width = 4;
323 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
324 break;
325 }
326
327 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
328 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
329 }
330
331 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
332 .dram_sdqs0 = 0x00003030,
333 .dram_sdqs1 = 0x00003030,
334 .dram_sdqs2 = 0x00003030,
335 .dram_sdqs3 = 0x00003030,
336 .dram_dqm0 = 0x00000030,
337 .dram_dqm1 = 0x00000030,
338 .dram_dqm2 = 0x00000030,
339 .dram_dqm3 = 0x00000030,
340 .dram_cas = 0x00000030,
341 .dram_ras = 0x00000030,
342 .dram_sdclk_0 = 0x00000028,
343 .dram_reset = 0x00000030,
344 .dram_sdba2 = 0x00000000,
345 .dram_odt0 = 0x00000008,
346 .dram_odt1 = 0x00000008,
347 };
348
349 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
350 .grp_b0ds = 0x00000030,
351 .grp_b1ds = 0x00000030,
352 .grp_b2ds = 0x00000030,
353 .grp_b3ds = 0x00000030,
354 .grp_addds = 0x00000030,
355 .grp_ctlds = 0x00000030,
356 .grp_ddrmode_ctl = 0x00020000,
357 .grp_ddrpke = 0x00000000,
358 .grp_ddrmode = 0x00020000,
359 .grp_ddr_type = 0x00080000,
360 };
361
362 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
363 .p0_mpdgctrl0 = 0x20000000,
364 .p0_mpdgctrl1 = 0x00000000,
365 .p0_mprddlctl = 0x4241444a,
366 .p0_mpwrdlctl = 0x3030312b,
367 .mpzqlp2ctl = 0x1b4700c7,
368 };
369
370 static struct mx6_lpddr2_cfg mem_ddr = {
371 .mem_speed = 800,
372 .density = 4,
373 .width = 32,
374 .banks = 8,
375 .rowaddr = 14,
376 .coladdr = 10,
377 .trcd_lp = 2000,
378 .trppb_lp = 2000,
379 .trpab_lp = 2250,
380 .trasmin = 4200,
381 };
382
ccgr_init(void)383 static void ccgr_init(void)
384 {
385 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
386
387 writel(0xFFFFFFFF, &ccm->CCGR0);
388 writel(0xFFFFFFFF, &ccm->CCGR1);
389 writel(0xFFFFFFFF, &ccm->CCGR2);
390 writel(0xFFFFFFFF, &ccm->CCGR3);
391 writel(0xFFFFFFFF, &ccm->CCGR4);
392 writel(0xFFFFFFFF, &ccm->CCGR5);
393 writel(0xFFFFFFFF, &ccm->CCGR6);
394
395 writel(0x00260324, &ccm->cbcmr);
396 }
397
spl_dram_init(void)398 static void spl_dram_init(void)
399 {
400 struct mx6_ddr_sysinfo sysinfo = {
401 .dsize = mem_ddr.width / 32,
402 .cs_density = 20,
403 .ncs = 2,
404 .cs1_mirror = 0,
405 .walat = 0,
406 .ralat = 2,
407 .mif3_mode = 3,
408 .bi_on = 1,
409 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
410 .rtt_nom = 0,
411 .sde_to_rst = 0, /* LPDDR2 does not need this field */
412 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
413 .ddr_type = DDR_TYPE_LPDDR2,
414 .refsel = 0, /* Refresh cycles at 64KHz */
415 .refr = 3, /* 4 refresh commands per refresh cycle */
416 };
417 mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
418 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
419 }
420
board_init_f(ulong dummy)421 void board_init_f(ulong dummy)
422 {
423 /* setup AIPS and disable watchdog */
424 arch_cpu_init();
425
426 ccgr_init();
427
428 /* iomux and setup of i2c */
429 board_early_init_f();
430
431 /* setup GP timer */
432 timer_init();
433
434 /* UART clocks enabled and gd valid - init serial console */
435 preloader_console_init();
436
437 /* DDR initialization */
438 spl_dram_init();
439
440 /* Clear the BSS. */
441 memset(__bss_start, 0, __bss_end - __bss_start);
442
443 /* load/boot image from boot device */
444 board_init_r(NULL, 0);
445 }
446 #endif
447