1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3 *
4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "vmwgfx_drv.h"
30
31 #include "vmwgfx_bo.h"
32 #include "vmwgfx_binding.h"
33 #include "vmwgfx_devcaps.h"
34 #include "vmwgfx_mksstat.h"
35 #include "ttm_object.h"
36
37 #include <drm/drm_aperture.h>
38 #include <drm/drm_drv.h>
39 #include <drm/drm_fbdev_generic.h>
40 #include <drm/drm_gem_ttm_helper.h>
41 #include <drm/drm_ioctl.h>
42 #include <drm/drm_module.h>
43 #include <drm/drm_sysfs.h>
44 #include <drm/ttm/ttm_range_manager.h>
45 #include <drm/ttm/ttm_placement.h>
46 #include <generated/utsrelease.h>
47
48 #ifdef CONFIG_X86
49 #include <asm/hypervisor.h>
50 #endif
51 #include <linux/cc_platform.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/version.h>
56
57 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
58
59 /*
60 * Fully encoded drm commands. Might move to vmw_drm.h
61 */
62
63 #define DRM_IOCTL_VMW_GET_PARAM \
64 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
65 struct drm_vmw_getparam_arg)
66 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
67 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
68 union drm_vmw_alloc_dmabuf_arg)
69 #define DRM_IOCTL_VMW_UNREF_DMABUF \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
71 struct drm_vmw_unref_dmabuf_arg)
72 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
74 struct drm_vmw_cursor_bypass_arg)
75
76 #define DRM_IOCTL_VMW_CONTROL_STREAM \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
78 struct drm_vmw_control_stream_arg)
79 #define DRM_IOCTL_VMW_CLAIM_STREAM \
80 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
81 struct drm_vmw_stream_arg)
82 #define DRM_IOCTL_VMW_UNREF_STREAM \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
84 struct drm_vmw_stream_arg)
85
86 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
87 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
88 struct drm_vmw_context_arg)
89 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
91 struct drm_vmw_context_arg)
92 #define DRM_IOCTL_VMW_CREATE_SURFACE \
93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
94 union drm_vmw_surface_create_arg)
95 #define DRM_IOCTL_VMW_UNREF_SURFACE \
96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
97 struct drm_vmw_surface_arg)
98 #define DRM_IOCTL_VMW_REF_SURFACE \
99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
100 union drm_vmw_surface_reference_arg)
101 #define DRM_IOCTL_VMW_EXECBUF \
102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
103 struct drm_vmw_execbuf_arg)
104 #define DRM_IOCTL_VMW_GET_3D_CAP \
105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
106 struct drm_vmw_get_3d_cap_arg)
107 #define DRM_IOCTL_VMW_FENCE_WAIT \
108 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
109 struct drm_vmw_fence_wait_arg)
110 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
111 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
112 struct drm_vmw_fence_signaled_arg)
113 #define DRM_IOCTL_VMW_FENCE_UNREF \
114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
115 struct drm_vmw_fence_arg)
116 #define DRM_IOCTL_VMW_FENCE_EVENT \
117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
118 struct drm_vmw_fence_event_arg)
119 #define DRM_IOCTL_VMW_PRESENT \
120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
121 struct drm_vmw_present_arg)
122 #define DRM_IOCTL_VMW_PRESENT_READBACK \
123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
124 struct drm_vmw_present_readback_arg)
125 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
127 struct drm_vmw_update_layout_arg)
128 #define DRM_IOCTL_VMW_CREATE_SHADER \
129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
130 struct drm_vmw_shader_create_arg)
131 #define DRM_IOCTL_VMW_UNREF_SHADER \
132 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
133 struct drm_vmw_shader_arg)
134 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
135 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
136 union drm_vmw_gb_surface_create_arg)
137 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
139 union drm_vmw_gb_surface_reference_arg)
140 #define DRM_IOCTL_VMW_SYNCCPU \
141 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
142 struct drm_vmw_synccpu_arg)
143 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
145 struct drm_vmw_context_arg)
146 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
148 union drm_vmw_gb_surface_create_ext_arg)
149 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
151 union drm_vmw_gb_surface_reference_ext_arg)
152 #define DRM_IOCTL_VMW_MSG \
153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
154 struct drm_vmw_msg_arg)
155 #define DRM_IOCTL_VMW_MKSSTAT_RESET \
156 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
157 #define DRM_IOCTL_VMW_MKSSTAT_ADD \
158 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \
159 struct drm_vmw_mksstat_add_arg)
160 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \
161 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \
162 struct drm_vmw_mksstat_remove_arg)
163
164 /*
165 * Ioctl definitions.
166 */
167
168 static const struct drm_ioctl_desc vmw_ioctls[] = {
169 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl,
170 DRM_RENDER_ALLOW),
171 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl,
172 DRM_RENDER_ALLOW),
173 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
174 DRM_RENDER_ALLOW),
175 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS,
176 vmw_kms_cursor_bypass_ioctl,
177 DRM_MASTER),
178
179 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
180 DRM_MASTER),
181 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
182 DRM_MASTER),
183 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
184 DRM_MASTER),
185
186 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
187 DRM_RENDER_ALLOW),
188 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
189 DRM_RENDER_ALLOW),
190 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
191 DRM_RENDER_ALLOW),
192 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
193 DRM_RENDER_ALLOW),
194 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
195 DRM_RENDER_ALLOW),
196 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl,
197 DRM_RENDER_ALLOW),
198 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
199 DRM_RENDER_ALLOW),
200 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED,
201 vmw_fence_obj_signaled_ioctl,
202 DRM_RENDER_ALLOW),
203 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
204 DRM_RENDER_ALLOW),
205 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
206 DRM_RENDER_ALLOW),
207 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
208 DRM_RENDER_ALLOW),
209
210 /* these allow direct access to the framebuffers mark as master only */
211 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl,
212 DRM_MASTER | DRM_AUTH),
213 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK,
214 vmw_present_readback_ioctl,
215 DRM_MASTER | DRM_AUTH),
216 /*
217 * The permissions of the below ioctl are overridden in
218 * vmw_generic_ioctl(). We require either
219 * DRM_MASTER or capable(CAP_SYS_ADMIN).
220 */
221 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT,
222 vmw_kms_update_layout_ioctl,
223 DRM_RENDER_ALLOW),
224 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER,
225 vmw_shader_define_ioctl,
226 DRM_RENDER_ALLOW),
227 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER,
228 vmw_shader_destroy_ioctl,
229 DRM_RENDER_ALLOW),
230 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE,
231 vmw_gb_surface_define_ioctl,
232 DRM_RENDER_ALLOW),
233 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF,
234 vmw_gb_surface_reference_ioctl,
235 DRM_RENDER_ALLOW),
236 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU,
237 vmw_user_bo_synccpu_ioctl,
238 DRM_RENDER_ALLOW),
239 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT,
240 vmw_extended_context_define_ioctl,
241 DRM_RENDER_ALLOW),
242 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT,
243 vmw_gb_surface_define_ext_ioctl,
244 DRM_RENDER_ALLOW),
245 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT,
246 vmw_gb_surface_reference_ext_ioctl,
247 DRM_RENDER_ALLOW),
248 DRM_IOCTL_DEF_DRV(VMW_MSG,
249 vmw_msg_ioctl,
250 DRM_RENDER_ALLOW),
251 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET,
252 vmw_mksstat_reset_ioctl,
253 DRM_RENDER_ALLOW),
254 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD,
255 vmw_mksstat_add_ioctl,
256 DRM_RENDER_ALLOW),
257 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE,
258 vmw_mksstat_remove_ioctl,
259 DRM_RENDER_ALLOW),
260 };
261
262 static const struct pci_device_id vmw_pci_id_list[] = {
263 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) },
264 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) },
265 { }
266 };
267 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
268
269 static int vmw_restrict_iommu;
270 static int vmw_force_coherent;
271 static int vmw_restrict_dma_mask;
272 static int vmw_assume_16bpp;
273
274 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
275 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
276 void *ptr);
277
278 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
279 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
280 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
281 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
282 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
283 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
284 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
285 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
286
287
288 struct bitmap_name {
289 uint32 value;
290 const char *name;
291 };
292
293 static const struct bitmap_name cap1_names[] = {
294 { SVGA_CAP_RECT_COPY, "rect copy" },
295 { SVGA_CAP_CURSOR, "cursor" },
296 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" },
297 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" },
298 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" },
299 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" },
300 { SVGA_CAP_3D, "3D" },
301 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" },
302 { SVGA_CAP_MULTIMON, "multimon" },
303 { SVGA_CAP_PITCHLOCK, "pitchlock" },
304 { SVGA_CAP_IRQMASK, "irq mask" },
305 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" },
306 { SVGA_CAP_GMR, "gmr" },
307 { SVGA_CAP_TRACES, "traces" },
308 { SVGA_CAP_GMR2, "gmr2" },
309 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" },
310 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" },
311 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" },
312 { SVGA_CAP_GBOBJECTS, "gbobject" },
313 { SVGA_CAP_DX, "dx" },
314 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" },
315 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" },
316 { SVGA_CAP_CAP2_REGISTER, "cap2 register" },
317 };
318
319
320 static const struct bitmap_name cap2_names[] = {
321 { SVGA_CAP2_GROW_OTABLE, "grow otable" },
322 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" },
323 { SVGA_CAP2_DX2, "dx2" },
324 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" },
325 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" },
326 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" },
327 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" },
328 { SVGA_CAP2_CURSOR_MOB, "cursor mob" },
329 { SVGA_CAP2_MSHINT, "mshint" },
330 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" },
331 { SVGA_CAP2_DX3, "dx3" },
332 { SVGA_CAP2_FRAME_TYPE, "frame type" },
333 { SVGA_CAP2_COTABLE_COPY, "cotable copy" },
334 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" },
335 { SVGA_CAP2_EXTRA_REGS, "extra regs" },
336 { SVGA_CAP2_LO_STAGING, "lo staging" },
337 };
338
vmw_print_bitmap(struct drm_device * drm,const char * prefix,uint32_t bitmap,const struct bitmap_name * bnames,uint32_t num_names)339 static void vmw_print_bitmap(struct drm_device *drm,
340 const char *prefix, uint32_t bitmap,
341 const struct bitmap_name *bnames,
342 uint32_t num_names)
343 {
344 char buf[512];
345 uint32_t i;
346 uint32_t offset = 0;
347 for (i = 0; i < num_names; ++i) {
348 if ((bitmap & bnames[i].value) != 0) {
349 offset += snprintf(buf + offset,
350 ARRAY_SIZE(buf) - offset,
351 "%s, ", bnames[i].name);
352 bitmap &= ~bnames[i].value;
353 }
354 }
355
356 drm_info(drm, "%s: %s\n", prefix, buf);
357 if (bitmap != 0)
358 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap);
359 }
360
361
vmw_print_sm_type(struct vmw_private * dev_priv)362 static void vmw_print_sm_type(struct vmw_private *dev_priv)
363 {
364 static const char *names[] = {
365 [VMW_SM_LEGACY] = "Legacy",
366 [VMW_SM_4] = "SM4",
367 [VMW_SM_4_1] = "SM4_1",
368 [VMW_SM_5] = "SM_5",
369 [VMW_SM_5_1X] = "SM_5_1X",
370 [VMW_SM_MAX] = "Invalid"
371 };
372 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1));
373 drm_info(&dev_priv->drm, "Available shader model: %s.\n",
374 names[dev_priv->sm_type]);
375 }
376
377 /**
378 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
379 *
380 * @dev_priv: A device private structure.
381 *
382 * This function creates a small buffer object that holds the query
383 * result for dummy queries emitted as query barriers.
384 * The function will then map the first page and initialize a pending
385 * occlusion query result structure, Finally it will unmap the buffer.
386 * No interruptible waits are done within this function.
387 *
388 * Returns an error if bo creation or initialization fails.
389 */
vmw_dummy_query_bo_create(struct vmw_private * dev_priv)390 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
391 {
392 int ret;
393 struct vmw_bo *vbo;
394 struct ttm_bo_kmap_obj map;
395 volatile SVGA3dQueryResult *result;
396 bool dummy;
397 struct vmw_bo_params bo_params = {
398 .domain = VMW_BO_DOMAIN_SYS,
399 .busy_domain = VMW_BO_DOMAIN_SYS,
400 .bo_type = ttm_bo_type_kernel,
401 .size = PAGE_SIZE,
402 .pin = true,
403 .keep_resv = true,
404 };
405
406 /*
407 * Create the vbo as pinned, so that a tryreserve will
408 * immediately succeed. This is because we're the only
409 * user of the bo currently.
410 */
411 ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
412 if (unlikely(ret != 0))
413 return ret;
414
415 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map);
416 if (likely(ret == 0)) {
417 result = ttm_kmap_obj_virtual(&map, &dummy);
418 result->totalSize = sizeof(*result);
419 result->state = SVGA3D_QUERYSTATE_PENDING;
420 result->result32 = 0xff;
421 ttm_bo_kunmap(&map);
422 }
423 vmw_bo_pin_reserved(vbo, false);
424 ttm_bo_unreserve(&vbo->tbo);
425
426 if (unlikely(ret != 0)) {
427 DRM_ERROR("Dummy query buffer map failed.\n");
428 vmw_bo_unreference(&vbo);
429 } else
430 dev_priv->dummy_query_bo = vbo;
431
432 return ret;
433 }
434
vmw_device_init(struct vmw_private * dev_priv)435 static int vmw_device_init(struct vmw_private *dev_priv)
436 {
437 bool uses_fb_traces = false;
438
439 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
440 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
441 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
442
443 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
444 SVGA_REG_ENABLE_HIDE);
445
446 uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
447 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
448
449 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
450 dev_priv->fifo = vmw_fifo_create(dev_priv);
451 if (IS_ERR(dev_priv->fifo)) {
452 int err = PTR_ERR(dev_priv->fifo);
453 dev_priv->fifo = NULL;
454 return err;
455 } else if (!dev_priv->fifo) {
456 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
457 }
458
459 dev_priv->last_read_seqno = vmw_fence_read(dev_priv);
460 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
461 return 0;
462 }
463
vmw_device_fini(struct vmw_private * vmw)464 static void vmw_device_fini(struct vmw_private *vmw)
465 {
466 /*
467 * Legacy sync
468 */
469 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
470 while (vmw_read(vmw, SVGA_REG_BUSY) != 0)
471 ;
472
473 vmw->last_read_seqno = vmw_fence_read(vmw);
474
475 vmw_write(vmw, SVGA_REG_CONFIG_DONE,
476 vmw->config_done_state);
477 vmw_write(vmw, SVGA_REG_ENABLE,
478 vmw->enable_state);
479 vmw_write(vmw, SVGA_REG_TRACES,
480 vmw->traces_state);
481
482 vmw_fifo_destroy(vmw);
483 }
484
485 /**
486 * vmw_request_device_late - Perform late device setup
487 *
488 * @dev_priv: Pointer to device private.
489 *
490 * This function performs setup of otables and enables large command
491 * buffer submission. These tasks are split out to a separate function
492 * because it reverts vmw_release_device_early and is intended to be used
493 * by an error path in the hibernation code.
494 */
vmw_request_device_late(struct vmw_private * dev_priv)495 static int vmw_request_device_late(struct vmw_private *dev_priv)
496 {
497 int ret;
498
499 if (dev_priv->has_mob) {
500 ret = vmw_otables_setup(dev_priv);
501 if (unlikely(ret != 0)) {
502 DRM_ERROR("Unable to initialize "
503 "guest Memory OBjects.\n");
504 return ret;
505 }
506 }
507
508 if (dev_priv->cman) {
509 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
510 if (ret) {
511 struct vmw_cmdbuf_man *man = dev_priv->cman;
512
513 dev_priv->cman = NULL;
514 vmw_cmdbuf_man_destroy(man);
515 }
516 }
517
518 return 0;
519 }
520
vmw_request_device(struct vmw_private * dev_priv)521 static int vmw_request_device(struct vmw_private *dev_priv)
522 {
523 int ret;
524
525 ret = vmw_device_init(dev_priv);
526 if (unlikely(ret != 0)) {
527 DRM_ERROR("Unable to initialize the device.\n");
528 return ret;
529 }
530 vmw_fence_fifo_up(dev_priv->fman);
531 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
532 if (IS_ERR(dev_priv->cman)) {
533 dev_priv->cman = NULL;
534 dev_priv->sm_type = VMW_SM_LEGACY;
535 }
536
537 ret = vmw_request_device_late(dev_priv);
538 if (ret)
539 goto out_no_mob;
540
541 ret = vmw_dummy_query_bo_create(dev_priv);
542 if (unlikely(ret != 0))
543 goto out_no_query_bo;
544
545 return 0;
546
547 out_no_query_bo:
548 if (dev_priv->cman)
549 vmw_cmdbuf_remove_pool(dev_priv->cman);
550 if (dev_priv->has_mob) {
551 struct ttm_resource_manager *man;
552
553 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
554 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
555 vmw_otables_takedown(dev_priv);
556 }
557 if (dev_priv->cman)
558 vmw_cmdbuf_man_destroy(dev_priv->cman);
559 out_no_mob:
560 vmw_fence_fifo_down(dev_priv->fman);
561 vmw_device_fini(dev_priv);
562 return ret;
563 }
564
565 /**
566 * vmw_release_device_early - Early part of fifo takedown.
567 *
568 * @dev_priv: Pointer to device private struct.
569 *
570 * This is the first part of command submission takedown, to be called before
571 * buffer management is taken down.
572 */
vmw_release_device_early(struct vmw_private * dev_priv)573 static void vmw_release_device_early(struct vmw_private *dev_priv)
574 {
575 /*
576 * Previous destructions should've released
577 * the pinned bo.
578 */
579
580 BUG_ON(dev_priv->pinned_bo != NULL);
581
582 vmw_bo_unreference(&dev_priv->dummy_query_bo);
583 if (dev_priv->cman)
584 vmw_cmdbuf_remove_pool(dev_priv->cman);
585
586 if (dev_priv->has_mob) {
587 struct ttm_resource_manager *man;
588
589 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
590 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
591 vmw_otables_takedown(dev_priv);
592 }
593 }
594
595 /**
596 * vmw_release_device_late - Late part of fifo takedown.
597 *
598 * @dev_priv: Pointer to device private struct.
599 *
600 * This is the last part of the command submission takedown, to be called when
601 * command submission is no longer needed. It may wait on pending fences.
602 */
vmw_release_device_late(struct vmw_private * dev_priv)603 static void vmw_release_device_late(struct vmw_private *dev_priv)
604 {
605 vmw_fence_fifo_down(dev_priv->fman);
606 if (dev_priv->cman)
607 vmw_cmdbuf_man_destroy(dev_priv->cman);
608
609 vmw_device_fini(dev_priv);
610 }
611
612 /*
613 * Sets the initial_[width|height] fields on the given vmw_private.
614 *
615 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
616 * clamping the value to fb_max_[width|height] fields and the
617 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
618 * If the values appear to be invalid, set them to
619 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
620 */
vmw_get_initial_size(struct vmw_private * dev_priv)621 static void vmw_get_initial_size(struct vmw_private *dev_priv)
622 {
623 uint32_t width;
624 uint32_t height;
625
626 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
627 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
628
629 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH);
630 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT);
631
632 if (width > dev_priv->fb_max_width ||
633 height > dev_priv->fb_max_height) {
634
635 /*
636 * This is a host error and shouldn't occur.
637 */
638
639 width = VMWGFX_MIN_INITIAL_WIDTH;
640 height = VMWGFX_MIN_INITIAL_HEIGHT;
641 }
642
643 dev_priv->initial_width = width;
644 dev_priv->initial_height = height;
645 }
646
647 /**
648 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
649 * system.
650 *
651 * @dev_priv: Pointer to a struct vmw_private
652 *
653 * This functions tries to determine what actions need to be taken by the
654 * driver to make system pages visible to the device.
655 * If this function decides that DMA is not possible, it returns -EINVAL.
656 * The driver may then try to disable features of the device that require
657 * DMA.
658 */
vmw_dma_select_mode(struct vmw_private * dev_priv)659 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
660 {
661 static const char *names[vmw_dma_map_max] = {
662 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
663 [vmw_dma_map_populate] = "Caching DMA mappings.",
664 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
665
666 /*
667 * When running with SEV we always want dma mappings, because
668 * otherwise ttm tt pool pages will bounce through swiotlb running
669 * out of available space.
670 */
671 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT))
672 dev_priv->map_mode = vmw_dma_alloc_coherent;
673 else if (vmw_restrict_iommu)
674 dev_priv->map_mode = vmw_dma_map_bind;
675 else
676 dev_priv->map_mode = vmw_dma_map_populate;
677
678 drm_info(&dev_priv->drm,
679 "DMA map mode: %s\n", names[dev_priv->map_mode]);
680 return 0;
681 }
682
683 /**
684 * vmw_dma_masks - set required page- and dma masks
685 *
686 * @dev_priv: Pointer to struct drm-device
687 *
688 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
689 * restriction also for 64-bit systems.
690 */
vmw_dma_masks(struct vmw_private * dev_priv)691 static int vmw_dma_masks(struct vmw_private *dev_priv)
692 {
693 struct drm_device *dev = &dev_priv->drm;
694 int ret = 0;
695
696 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
697 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
698 drm_info(&dev_priv->drm,
699 "Restricting DMA addresses to 44 bits.\n");
700 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
701 }
702
703 return ret;
704 }
705
vmw_vram_manager_init(struct vmw_private * dev_priv)706 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
707 {
708 int ret;
709 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
710 dev_priv->vram_size >> PAGE_SHIFT);
711 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
712 return ret;
713 }
714
vmw_vram_manager_fini(struct vmw_private * dev_priv)715 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
716 {
717 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
718 }
719
vmw_setup_pci_resources(struct vmw_private * dev,u32 pci_id)720 static int vmw_setup_pci_resources(struct vmw_private *dev,
721 u32 pci_id)
722 {
723 resource_size_t rmmio_start;
724 resource_size_t rmmio_size;
725 resource_size_t fifo_start;
726 resource_size_t fifo_size;
727 int ret;
728 struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
729
730 pci_set_master(pdev);
731
732 ret = pci_request_regions(pdev, "vmwgfx probe");
733 if (ret)
734 return ret;
735
736 dev->pci_id = pci_id;
737 if (pci_id == VMWGFX_PCI_ID_SVGA3) {
738 rmmio_start = pci_resource_start(pdev, 0);
739 rmmio_size = pci_resource_len(pdev, 0);
740 dev->vram_start = pci_resource_start(pdev, 2);
741 dev->vram_size = pci_resource_len(pdev, 2);
742
743 drm_info(&dev->drm,
744 "Register MMIO at 0x%pa size is %llu kiB\n",
745 &rmmio_start, (uint64_t)rmmio_size / 1024);
746 dev->rmmio = devm_ioremap(dev->drm.dev,
747 rmmio_start,
748 rmmio_size);
749 if (!dev->rmmio) {
750 drm_err(&dev->drm,
751 "Failed mapping registers mmio memory.\n");
752 pci_release_regions(pdev);
753 return -ENOMEM;
754 }
755 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) {
756 dev->io_start = pci_resource_start(pdev, 0);
757 dev->vram_start = pci_resource_start(pdev, 1);
758 dev->vram_size = pci_resource_len(pdev, 1);
759 fifo_start = pci_resource_start(pdev, 2);
760 fifo_size = pci_resource_len(pdev, 2);
761
762 drm_info(&dev->drm,
763 "FIFO at %pa size is %llu kiB\n",
764 &fifo_start, (uint64_t)fifo_size / 1024);
765 dev->fifo_mem = devm_memremap(dev->drm.dev,
766 fifo_start,
767 fifo_size,
768 MEMREMAP_WB);
769
770 if (IS_ERR(dev->fifo_mem)) {
771 drm_err(&dev->drm,
772 "Failed mapping FIFO memory.\n");
773 pci_release_regions(pdev);
774 return PTR_ERR(dev->fifo_mem);
775 }
776 } else {
777 pci_release_regions(pdev);
778 return -EINVAL;
779 }
780
781 /*
782 * This is approximate size of the vram, the exact size will only
783 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
784 * size will be equal to or bigger than the size reported by
785 * SVGA_REG_VRAM_SIZE.
786 */
787 drm_info(&dev->drm,
788 "VRAM at %pa size is %llu kiB\n",
789 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
790
791 return 0;
792 }
793
vmw_detect_version(struct vmw_private * dev)794 static int vmw_detect_version(struct vmw_private *dev)
795 {
796 uint32_t svga_id;
797
798 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ?
799 SVGA_ID_3 : SVGA_ID_2);
800 svga_id = vmw_read(dev, SVGA_REG_ID);
801 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
802 drm_err(&dev->drm,
803 "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
804 svga_id, dev->pci_id);
805 return -ENOSYS;
806 }
807 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
808 drm_info(&dev->drm,
809 "Running on SVGA version %d.\n", (svga_id & 0xff));
810 return 0;
811 }
812
vmw_write_driver_id(struct vmw_private * dev)813 static void vmw_write_driver_id(struct vmw_private *dev)
814 {
815 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) {
816 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
817 SVGA_REG_GUEST_DRIVER_ID_LINUX);
818
819 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1,
820 LINUX_VERSION_MAJOR << 24 |
821 LINUX_VERSION_PATCHLEVEL << 16 |
822 LINUX_VERSION_SUBLEVEL);
823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2,
824 VMWGFX_DRIVER_MAJOR << 24 |
825 VMWGFX_DRIVER_MINOR << 16 |
826 VMWGFX_DRIVER_PATCHLEVEL);
827 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0);
828
829 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
830 SVGA_REG_GUEST_DRIVER_ID_SUBMIT);
831 }
832 }
833
vmw_sw_context_init(struct vmw_private * dev_priv)834 static void vmw_sw_context_init(struct vmw_private *dev_priv)
835 {
836 struct vmw_sw_context *sw_context = &dev_priv->ctx;
837
838 hash_init(sw_context->res_ht);
839 }
840
vmw_sw_context_fini(struct vmw_private * dev_priv)841 static void vmw_sw_context_fini(struct vmw_private *dev_priv)
842 {
843 struct vmw_sw_context *sw_context = &dev_priv->ctx;
844
845 vfree(sw_context->cmd_bounce);
846 if (sw_context->staged_bindings)
847 vmw_binding_state_free(sw_context->staged_bindings);
848 }
849
vmw_driver_load(struct vmw_private * dev_priv,u32 pci_id)850 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
851 {
852 int ret;
853 enum vmw_res_type i;
854 bool refuse_dma = false;
855 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
856
857 dev_priv->drm.dev_private = dev_priv;
858
859 vmw_sw_context_init(dev_priv);
860
861 mutex_init(&dev_priv->cmdbuf_mutex);
862 mutex_init(&dev_priv->binding_mutex);
863 spin_lock_init(&dev_priv->resource_lock);
864 spin_lock_init(&dev_priv->hw_lock);
865 spin_lock_init(&dev_priv->waiter_lock);
866 spin_lock_init(&dev_priv->cursor_lock);
867
868 ret = vmw_setup_pci_resources(dev_priv, pci_id);
869 if (ret)
870 return ret;
871 ret = vmw_detect_version(dev_priv);
872 if (ret)
873 goto out_no_pci_or_version;
874
875
876 for (i = vmw_res_context; i < vmw_res_max; ++i) {
877 idr_init_base(&dev_priv->res_idr[i], 1);
878 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
879 }
880
881 init_waitqueue_head(&dev_priv->fence_queue);
882 init_waitqueue_head(&dev_priv->fifo_queue);
883 dev_priv->fence_queue_waiters = 0;
884 dev_priv->fifo_queue_waiters = 0;
885
886 dev_priv->used_memory_size = 0;
887
888 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
889
890 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
891 vmw_print_bitmap(&dev_priv->drm, "Capabilities",
892 dev_priv->capabilities,
893 cap1_names, ARRAY_SIZE(cap1_names));
894 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
895 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
896 vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
897 dev_priv->capabilities2,
898 cap2_names, ARRAY_SIZE(cap2_names));
899 }
900
901 if (!vmwgfx_supported(dev_priv)) {
902 vmw_disable_backdoor();
903 drm_err_once(&dev_priv->drm,
904 "vmwgfx seems to be running on an unsupported hypervisor.");
905 drm_err_once(&dev_priv->drm,
906 "This configuration is likely broken.");
907 drm_err_once(&dev_priv->drm,
908 "Please switch to a supported graphics device to avoid problems.");
909 }
910
911 ret = vmw_dma_select_mode(dev_priv);
912 if (unlikely(ret != 0)) {
913 drm_info(&dev_priv->drm,
914 "Restricting capabilities since DMA not available.\n");
915 refuse_dma = true;
916 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
917 drm_info(&dev_priv->drm,
918 "Disabling 3D acceleration.\n");
919 }
920
921 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
922 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
923 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
924 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
925
926 vmw_get_initial_size(dev_priv);
927
928 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
929 dev_priv->max_gmr_ids =
930 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
931 dev_priv->max_gmr_pages =
932 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
933 dev_priv->memory_size =
934 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
935 dev_priv->memory_size -= dev_priv->vram_size;
936 } else {
937 /*
938 * An arbitrary limit of 512MiB on surface
939 * memory. But all HWV8 hardware supports GMR2.
940 */
941 dev_priv->memory_size = 512*1024*1024;
942 }
943 dev_priv->max_mob_pages = 0;
944 dev_priv->max_mob_size = 0;
945 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
946 uint64_t mem_size;
947
948 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
949 mem_size = vmw_read(dev_priv,
950 SVGA_REG_GBOBJECT_MEM_SIZE_KB);
951 else
952 mem_size =
953 vmw_read(dev_priv,
954 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
955
956 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
957 dev_priv->max_primary_mem =
958 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
959 dev_priv->max_mob_size =
960 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
961 dev_priv->stdu_max_width =
962 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
963 dev_priv->stdu_max_height =
964 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
965
966 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
967 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
968 dev_priv->texture_max_width = vmw_read(dev_priv,
969 SVGA_REG_DEV_CAP);
970 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
971 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
972 dev_priv->texture_max_height = vmw_read(dev_priv,
973 SVGA_REG_DEV_CAP);
974 } else {
975 dev_priv->texture_max_width = 8192;
976 dev_priv->texture_max_height = 8192;
977 dev_priv->max_primary_mem = dev_priv->vram_size;
978 }
979 drm_info(&dev_priv->drm,
980 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n",
981 (u64)dev_priv->vram_size / 1024,
982 (u64)dev_priv->fifo_mem_size / 1024,
983 dev_priv->memory_size / 1024);
984
985 drm_info(&dev_priv->drm,
986 "MOB limits: max mob size = %u kB, max mob pages = %u\n",
987 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
988
989 ret = vmw_dma_masks(dev_priv);
990 if (unlikely(ret != 0))
991 goto out_err0;
992
993 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
994
995 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
996 drm_info(&dev_priv->drm,
997 "Max GMR ids is %u\n",
998 (unsigned)dev_priv->max_gmr_ids);
999 drm_info(&dev_priv->drm,
1000 "Max number of GMR pages is %u\n",
1001 (unsigned)dev_priv->max_gmr_pages);
1002 }
1003 drm_info(&dev_priv->drm,
1004 "Maximum display memory size is %llu kiB\n",
1005 (uint64_t)dev_priv->max_primary_mem / 1024);
1006
1007 /* Need mmio memory to check for fifo pitchlock cap. */
1008 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
1009 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
1010 !vmw_fifo_have_pitchlock(dev_priv)) {
1011 ret = -ENOSYS;
1012 DRM_ERROR("Hardware has no pitchlock\n");
1013 goto out_err0;
1014 }
1015
1016 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);
1017
1018 if (unlikely(dev_priv->tdev == NULL)) {
1019 drm_err(&dev_priv->drm,
1020 "Unable to initialize TTM object management.\n");
1021 ret = -ENOMEM;
1022 goto out_err0;
1023 }
1024
1025 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
1026 ret = vmw_irq_install(dev_priv);
1027 if (ret != 0) {
1028 drm_err(&dev_priv->drm,
1029 "Failed installing irq: %d\n", ret);
1030 goto out_no_irq;
1031 }
1032 }
1033
1034 dev_priv->fman = vmw_fence_manager_init(dev_priv);
1035 if (unlikely(dev_priv->fman == NULL)) {
1036 ret = -ENOMEM;
1037 goto out_no_fman;
1038 }
1039
1040 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
1041 dev_priv->drm.dev,
1042 dev_priv->drm.anon_inode->i_mapping,
1043 dev_priv->drm.vma_offset_manager,
1044 dev_priv->map_mode == vmw_dma_alloc_coherent,
1045 false);
1046 if (unlikely(ret != 0)) {
1047 drm_err(&dev_priv->drm,
1048 "Failed initializing TTM buffer object driver.\n");
1049 goto out_no_bdev;
1050 }
1051
1052 /*
1053 * Enable VRAM, but initially don't use it until SVGA is enabled and
1054 * unhidden.
1055 */
1056
1057 ret = vmw_vram_manager_init(dev_priv);
1058 if (unlikely(ret != 0)) {
1059 drm_err(&dev_priv->drm,
1060 "Failed initializing memory manager for VRAM.\n");
1061 goto out_no_vram;
1062 }
1063
1064 ret = vmw_devcaps_create(dev_priv);
1065 if (unlikely(ret != 0)) {
1066 drm_err(&dev_priv->drm,
1067 "Failed initializing device caps.\n");
1068 goto out_no_vram;
1069 }
1070
1071 /*
1072 * "Guest Memory Regions" is an aperture like feature with
1073 * one slot per bo. There is an upper limit of the number of
1074 * slots as well as the bo size.
1075 */
1076 dev_priv->has_gmr = true;
1077 /* TODO: This is most likely not correct */
1078 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1079 refuse_dma ||
1080 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1081 drm_info(&dev_priv->drm,
1082 "No GMR memory available. "
1083 "Graphics memory resources are very limited.\n");
1084 dev_priv->has_gmr = false;
1085 }
1086
1087 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1088 dev_priv->has_mob = true;
1089
1090 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1091 drm_info(&dev_priv->drm,
1092 "No MOB memory available. "
1093 "3D will be disabled.\n");
1094 dev_priv->has_mob = false;
1095 }
1096 if (vmw_sys_man_init(dev_priv) != 0) {
1097 drm_info(&dev_priv->drm,
1098 "No MOB page table memory available. "
1099 "3D will be disabled.\n");
1100 dev_priv->has_mob = false;
1101 }
1102 }
1103
1104 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1105 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1106 dev_priv->sm_type = VMW_SM_4;
1107 }
1108
1109 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1110 if (has_sm4_context(dev_priv) &&
1111 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1112 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1113 dev_priv->sm_type = VMW_SM_4_1;
1114 if (has_sm4_1_context(dev_priv) &&
1115 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1116 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {
1117 dev_priv->sm_type = VMW_SM_5;
1118 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))
1119 dev_priv->sm_type = VMW_SM_5_1X;
1120 }
1121 }
1122 }
1123
1124 ret = vmw_kms_init(dev_priv);
1125 if (unlikely(ret != 0))
1126 goto out_no_kms;
1127 vmw_overlay_init(dev_priv);
1128
1129 ret = vmw_request_device(dev_priv);
1130 if (ret)
1131 goto out_no_fifo;
1132
1133 vmw_print_sm_type(dev_priv);
1134 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1135 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
1136 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
1137 vmw_write_driver_id(dev_priv);
1138
1139 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1140 register_pm_notifier(&dev_priv->pm_nb);
1141
1142 return 0;
1143
1144 out_no_fifo:
1145 vmw_overlay_close(dev_priv);
1146 vmw_kms_close(dev_priv);
1147 out_no_kms:
1148 if (dev_priv->has_mob) {
1149 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1150 vmw_sys_man_fini(dev_priv);
1151 }
1152 if (dev_priv->has_gmr)
1153 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1154 vmw_devcaps_destroy(dev_priv);
1155 vmw_vram_manager_fini(dev_priv);
1156 out_no_vram:
1157 ttm_device_fini(&dev_priv->bdev);
1158 out_no_bdev:
1159 vmw_fence_manager_takedown(dev_priv->fman);
1160 out_no_fman:
1161 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1162 vmw_irq_uninstall(&dev_priv->drm);
1163 out_no_irq:
1164 ttm_object_device_release(&dev_priv->tdev);
1165 out_err0:
1166 for (i = vmw_res_context; i < vmw_res_max; ++i)
1167 idr_destroy(&dev_priv->res_idr[i]);
1168
1169 if (dev_priv->ctx.staged_bindings)
1170 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1171 out_no_pci_or_version:
1172 pci_release_regions(pdev);
1173 return ret;
1174 }
1175
vmw_driver_unload(struct drm_device * dev)1176 static void vmw_driver_unload(struct drm_device *dev)
1177 {
1178 struct vmw_private *dev_priv = vmw_priv(dev);
1179 struct pci_dev *pdev = to_pci_dev(dev->dev);
1180 enum vmw_res_type i;
1181
1182 unregister_pm_notifier(&dev_priv->pm_nb);
1183
1184 vmw_sw_context_fini(dev_priv);
1185 vmw_fifo_resource_dec(dev_priv);
1186
1187 vmw_svga_disable(dev_priv);
1188
1189 vmw_kms_close(dev_priv);
1190 vmw_overlay_close(dev_priv);
1191
1192 if (dev_priv->has_gmr)
1193 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1194
1195 vmw_release_device_early(dev_priv);
1196 if (dev_priv->has_mob) {
1197 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1198 vmw_sys_man_fini(dev_priv);
1199 }
1200 vmw_devcaps_destroy(dev_priv);
1201 vmw_vram_manager_fini(dev_priv);
1202 ttm_device_fini(&dev_priv->bdev);
1203 vmw_release_device_late(dev_priv);
1204 vmw_fence_manager_takedown(dev_priv->fman);
1205 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1206 vmw_irq_uninstall(&dev_priv->drm);
1207
1208 ttm_object_device_release(&dev_priv->tdev);
1209
1210 for (i = vmw_res_context; i < vmw_res_max; ++i)
1211 idr_destroy(&dev_priv->res_idr[i]);
1212
1213 vmw_mksstat_remove_all(dev_priv);
1214
1215 pci_release_regions(pdev);
1216 }
1217
vmw_postclose(struct drm_device * dev,struct drm_file * file_priv)1218 static void vmw_postclose(struct drm_device *dev,
1219 struct drm_file *file_priv)
1220 {
1221 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1222
1223 ttm_object_file_release(&vmw_fp->tfile);
1224 kfree(vmw_fp);
1225 }
1226
vmw_driver_open(struct drm_device * dev,struct drm_file * file_priv)1227 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1228 {
1229 struct vmw_private *dev_priv = vmw_priv(dev);
1230 struct vmw_fpriv *vmw_fp;
1231 int ret = -ENOMEM;
1232
1233 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1234 if (unlikely(!vmw_fp))
1235 return ret;
1236
1237 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);
1238 if (unlikely(vmw_fp->tfile == NULL))
1239 goto out_no_tfile;
1240
1241 file_priv->driver_priv = vmw_fp;
1242
1243 return 0;
1244
1245 out_no_tfile:
1246 kfree(vmw_fp);
1247 return ret;
1248 }
1249
vmw_generic_ioctl(struct file * filp,unsigned int cmd,unsigned long arg,long (* ioctl_func)(struct file *,unsigned int,unsigned long))1250 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1251 unsigned long arg,
1252 long (*ioctl_func)(struct file *, unsigned int,
1253 unsigned long))
1254 {
1255 struct drm_file *file_priv = filp->private_data;
1256 struct drm_device *dev = file_priv->minor->dev;
1257 unsigned int nr = DRM_IOCTL_NR(cmd);
1258 unsigned int flags;
1259
1260 /*
1261 * Do extra checking on driver private ioctls.
1262 */
1263
1264 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1265 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1266 const struct drm_ioctl_desc *ioctl =
1267 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1268
1269 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1270 return ioctl_func(filp, cmd, arg);
1271 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1272 if (!drm_is_current_master(file_priv) &&
1273 !capable(CAP_SYS_ADMIN))
1274 return -EACCES;
1275 }
1276
1277 if (unlikely(ioctl->cmd != cmd))
1278 goto out_io_encoding;
1279
1280 flags = ioctl->flags;
1281 } else if (!drm_ioctl_flags(nr, &flags))
1282 return -EINVAL;
1283
1284 return ioctl_func(filp, cmd, arg);
1285
1286 out_io_encoding:
1287 DRM_ERROR("Invalid command format, ioctl %d\n",
1288 nr - DRM_COMMAND_BASE);
1289
1290 return -EINVAL;
1291 }
1292
vmw_unlocked_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1293 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1294 unsigned long arg)
1295 {
1296 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1297 }
1298
1299 #ifdef CONFIG_COMPAT
vmw_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1300 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1301 unsigned long arg)
1302 {
1303 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1304 }
1305 #endif
1306
vmw_master_set(struct drm_device * dev,struct drm_file * file_priv,bool from_open)1307 static void vmw_master_set(struct drm_device *dev,
1308 struct drm_file *file_priv,
1309 bool from_open)
1310 {
1311 /*
1312 * Inform a new master that the layout may have changed while
1313 * it was gone.
1314 */
1315 if (!from_open)
1316 drm_sysfs_hotplug_event(dev);
1317 }
1318
vmw_master_drop(struct drm_device * dev,struct drm_file * file_priv)1319 static void vmw_master_drop(struct drm_device *dev,
1320 struct drm_file *file_priv)
1321 {
1322 struct vmw_private *dev_priv = vmw_priv(dev);
1323
1324 vmw_kms_legacy_hotspot_clear(dev_priv);
1325 }
1326
vmwgfx_supported(struct vmw_private * vmw)1327 bool vmwgfx_supported(struct vmw_private *vmw)
1328 {
1329 #if defined(CONFIG_X86)
1330 return hypervisor_is_type(X86_HYPER_VMWARE);
1331 #elif defined(CONFIG_ARM64)
1332 /*
1333 * On aarch64 only svga3 is supported
1334 */
1335 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3;
1336 #else
1337 drm_warn_once(&vmw->drm,
1338 "vmwgfx is running on an unknown architecture.");
1339 return false;
1340 #endif
1341 }
1342
1343 /**
1344 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1345 *
1346 * @dev_priv: Pointer to device private struct.
1347 * Needs the reservation sem to be held in non-exclusive mode.
1348 */
__vmw_svga_enable(struct vmw_private * dev_priv)1349 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1350 {
1351 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1352
1353 if (!ttm_resource_manager_used(man)) {
1354 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1355 ttm_resource_manager_set_used(man, true);
1356 }
1357 }
1358
1359 /**
1360 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1361 *
1362 * @dev_priv: Pointer to device private struct.
1363 */
vmw_svga_enable(struct vmw_private * dev_priv)1364 void vmw_svga_enable(struct vmw_private *dev_priv)
1365 {
1366 __vmw_svga_enable(dev_priv);
1367 }
1368
1369 /**
1370 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1371 *
1372 * @dev_priv: Pointer to device private struct.
1373 * Needs the reservation sem to be held in exclusive mode.
1374 * Will not empty VRAM. VRAM must be emptied by caller.
1375 */
__vmw_svga_disable(struct vmw_private * dev_priv)1376 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1377 {
1378 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1379
1380 if (ttm_resource_manager_used(man)) {
1381 ttm_resource_manager_set_used(man, false);
1382 vmw_write(dev_priv, SVGA_REG_ENABLE,
1383 SVGA_REG_ENABLE_HIDE |
1384 SVGA_REG_ENABLE_ENABLE);
1385 }
1386 }
1387
1388 /**
1389 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1390 * running.
1391 *
1392 * @dev_priv: Pointer to device private struct.
1393 * Will empty VRAM.
1394 */
vmw_svga_disable(struct vmw_private * dev_priv)1395 void vmw_svga_disable(struct vmw_private *dev_priv)
1396 {
1397 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1398 /*
1399 * Disabling SVGA will turn off device modesetting capabilities, so
1400 * notify KMS about that so that it doesn't cache atomic state that
1401 * isn't valid anymore, for example crtcs turned on.
1402 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1403 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1404 * end up with lock order reversal. Thus, a master may actually perform
1405 * a new modeset just after we call vmw_kms_lost_device() and race with
1406 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1407 * to be inconsistent with the device, causing modesetting problems.
1408 *
1409 */
1410 vmw_kms_lost_device(&dev_priv->drm);
1411 if (ttm_resource_manager_used(man)) {
1412 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1413 DRM_ERROR("Failed evicting VRAM buffers.\n");
1414 ttm_resource_manager_set_used(man, false);
1415 vmw_write(dev_priv, SVGA_REG_ENABLE,
1416 SVGA_REG_ENABLE_HIDE |
1417 SVGA_REG_ENABLE_ENABLE);
1418 }
1419 }
1420
vmw_remove(struct pci_dev * pdev)1421 static void vmw_remove(struct pci_dev *pdev)
1422 {
1423 struct drm_device *dev = pci_get_drvdata(pdev);
1424
1425 drm_dev_unregister(dev);
1426 vmw_driver_unload(dev);
1427 }
1428
vmw_debugfs_resource_managers_init(struct vmw_private * vmw)1429 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw)
1430 {
1431 struct drm_minor *minor = vmw->drm.primary;
1432 struct dentry *root = minor->debugfs_root;
1433
1434 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM),
1435 root, "system_ttm");
1436 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM),
1437 root, "vram_ttm");
1438 if (vmw->has_gmr)
1439 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR),
1440 root, "gmr_ttm");
1441 if (vmw->has_mob) {
1442 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB),
1443 root, "mob_ttm");
1444 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM),
1445 root, "system_mob_ttm");
1446 }
1447 }
1448
vmwgfx_pm_notifier(struct notifier_block * nb,unsigned long val,void * ptr)1449 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1450 void *ptr)
1451 {
1452 struct vmw_private *dev_priv =
1453 container_of(nb, struct vmw_private, pm_nb);
1454
1455 switch (val) {
1456 case PM_HIBERNATION_PREPARE:
1457 /*
1458 * Take the reservation sem in write mode, which will make sure
1459 * there are no other processes holding a buffer object
1460 * reservation, meaning we should be able to evict all buffer
1461 * objects if needed.
1462 * Once user-space processes have been frozen, we can release
1463 * the lock again.
1464 */
1465 dev_priv->suspend_locked = true;
1466 break;
1467 case PM_POST_HIBERNATION:
1468 case PM_POST_RESTORE:
1469 if (READ_ONCE(dev_priv->suspend_locked)) {
1470 dev_priv->suspend_locked = false;
1471 }
1472 break;
1473 default:
1474 break;
1475 }
1476 return 0;
1477 }
1478
vmw_pci_suspend(struct pci_dev * pdev,pm_message_t state)1479 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1480 {
1481 struct drm_device *dev = pci_get_drvdata(pdev);
1482 struct vmw_private *dev_priv = vmw_priv(dev);
1483
1484 if (dev_priv->refuse_hibernation)
1485 return -EBUSY;
1486
1487 pci_save_state(pdev);
1488 pci_disable_device(pdev);
1489 pci_set_power_state(pdev, PCI_D3hot);
1490 return 0;
1491 }
1492
vmw_pci_resume(struct pci_dev * pdev)1493 static int vmw_pci_resume(struct pci_dev *pdev)
1494 {
1495 pci_set_power_state(pdev, PCI_D0);
1496 pci_restore_state(pdev);
1497 return pci_enable_device(pdev);
1498 }
1499
vmw_pm_suspend(struct device * kdev)1500 static int vmw_pm_suspend(struct device *kdev)
1501 {
1502 struct pci_dev *pdev = to_pci_dev(kdev);
1503 struct pm_message dummy;
1504
1505 dummy.event = 0;
1506
1507 return vmw_pci_suspend(pdev, dummy);
1508 }
1509
vmw_pm_resume(struct device * kdev)1510 static int vmw_pm_resume(struct device *kdev)
1511 {
1512 struct pci_dev *pdev = to_pci_dev(kdev);
1513
1514 return vmw_pci_resume(pdev);
1515 }
1516
vmw_pm_freeze(struct device * kdev)1517 static int vmw_pm_freeze(struct device *kdev)
1518 {
1519 struct pci_dev *pdev = to_pci_dev(kdev);
1520 struct drm_device *dev = pci_get_drvdata(pdev);
1521 struct vmw_private *dev_priv = vmw_priv(dev);
1522 struct ttm_operation_ctx ctx = {
1523 .interruptible = false,
1524 .no_wait_gpu = false
1525 };
1526 int ret;
1527
1528 /*
1529 * No user-space processes should be running now.
1530 */
1531 ret = vmw_kms_suspend(&dev_priv->drm);
1532 if (ret) {
1533 DRM_ERROR("Failed to freeze modesetting.\n");
1534 return ret;
1535 }
1536
1537 vmw_execbuf_release_pinned_bo(dev_priv);
1538 vmw_resource_evict_all(dev_priv);
1539 vmw_release_device_early(dev_priv);
1540 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1541 vmw_fifo_resource_dec(dev_priv);
1542 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1543 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1544 vmw_fifo_resource_inc(dev_priv);
1545 WARN_ON(vmw_request_device_late(dev_priv));
1546 dev_priv->suspend_locked = false;
1547 if (dev_priv->suspend_state)
1548 vmw_kms_resume(dev);
1549 return -EBUSY;
1550 }
1551
1552 vmw_fence_fifo_down(dev_priv->fman);
1553 __vmw_svga_disable(dev_priv);
1554
1555 vmw_release_device_late(dev_priv);
1556 return 0;
1557 }
1558
vmw_pm_restore(struct device * kdev)1559 static int vmw_pm_restore(struct device *kdev)
1560 {
1561 struct pci_dev *pdev = to_pci_dev(kdev);
1562 struct drm_device *dev = pci_get_drvdata(pdev);
1563 struct vmw_private *dev_priv = vmw_priv(dev);
1564 int ret;
1565
1566 vmw_detect_version(dev_priv);
1567
1568 vmw_fifo_resource_inc(dev_priv);
1569
1570 ret = vmw_request_device(dev_priv);
1571 if (ret)
1572 return ret;
1573
1574 __vmw_svga_enable(dev_priv);
1575
1576 vmw_fence_fifo_up(dev_priv->fman);
1577 dev_priv->suspend_locked = false;
1578 if (dev_priv->suspend_state)
1579 vmw_kms_resume(&dev_priv->drm);
1580
1581 return 0;
1582 }
1583
1584 static const struct dev_pm_ops vmw_pm_ops = {
1585 .freeze = vmw_pm_freeze,
1586 .thaw = vmw_pm_restore,
1587 .restore = vmw_pm_restore,
1588 .suspend = vmw_pm_suspend,
1589 .resume = vmw_pm_resume,
1590 };
1591
1592 static const struct file_operations vmwgfx_driver_fops = {
1593 .owner = THIS_MODULE,
1594 .open = drm_open,
1595 .release = drm_release,
1596 .unlocked_ioctl = vmw_unlocked_ioctl,
1597 .mmap = drm_gem_mmap,
1598 .poll = drm_poll,
1599 .read = drm_read,
1600 #if defined(CONFIG_COMPAT)
1601 .compat_ioctl = vmw_compat_ioctl,
1602 #endif
1603 .llseek = noop_llseek,
1604 };
1605
1606 static const struct drm_driver driver = {
1607 .driver_features =
1608 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT,
1609 .ioctls = vmw_ioctls,
1610 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1611 .master_set = vmw_master_set,
1612 .master_drop = vmw_master_drop,
1613 .open = vmw_driver_open,
1614 .postclose = vmw_postclose,
1615
1616 .dumb_create = vmw_dumb_create,
1617 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1618
1619 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1620 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1621 .gem_prime_import_sg_table = vmw_prime_import_sg_table,
1622
1623 .fops = &vmwgfx_driver_fops,
1624 .name = VMWGFX_DRIVER_NAME,
1625 .desc = VMWGFX_DRIVER_DESC,
1626 .date = VMWGFX_DRIVER_DATE,
1627 .major = VMWGFX_DRIVER_MAJOR,
1628 .minor = VMWGFX_DRIVER_MINOR,
1629 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1630 };
1631
1632 static struct pci_driver vmw_pci_driver = {
1633 .name = VMWGFX_DRIVER_NAME,
1634 .id_table = vmw_pci_id_list,
1635 .probe = vmw_probe,
1636 .remove = vmw_remove,
1637 .driver = {
1638 .pm = &vmw_pm_ops
1639 }
1640 };
1641
vmw_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1642 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1643 {
1644 struct vmw_private *vmw;
1645 int ret;
1646
1647 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver);
1648 if (ret)
1649 goto out_error;
1650
1651 ret = pcim_enable_device(pdev);
1652 if (ret)
1653 goto out_error;
1654
1655 vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1656 struct vmw_private, drm);
1657 if (IS_ERR(vmw)) {
1658 ret = PTR_ERR(vmw);
1659 goto out_error;
1660 }
1661
1662 pci_set_drvdata(pdev, &vmw->drm);
1663
1664 ret = vmw_driver_load(vmw, ent->device);
1665 if (ret)
1666 goto out_error;
1667
1668 ret = drm_dev_register(&vmw->drm, 0);
1669 if (ret)
1670 goto out_unload;
1671
1672 vmw_fifo_resource_inc(vmw);
1673 vmw_svga_enable(vmw);
1674 drm_fbdev_generic_setup(&vmw->drm, 0);
1675
1676 vmw_debugfs_gem_init(vmw);
1677 vmw_debugfs_resource_managers_init(vmw);
1678
1679 return 0;
1680 out_unload:
1681 vmw_driver_unload(&vmw->drm);
1682 out_error:
1683 return ret;
1684 }
1685
1686 drm_module_pci_driver(vmw_pci_driver);
1687
1688 MODULE_AUTHOR("VMware Inc. and others");
1689 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1690 MODULE_LICENSE("GPL and additional rights");
1691 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1692 __stringify(VMWGFX_DRIVER_MINOR) "."
1693 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1694 "0");
1695