| /openbmc/qemu/include/hw/i2c/ |
| H A D | smbus_eeprom.h | 33 enum sdram_type { SDR = 0x4, DDR = 0x7, DDR2 = 0x8 }; enumerator
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| /openbmc/linux/Documentation/accel/qaic/ |
| H A D | aic100.rst | 98 DDR section in Hardware Description
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| /openbmc/u-boot/drivers/video/ |
| H A D | bus_vcxk.c | 23 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
44 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/ |
| H A D | spr_misc.c | 19 #define DDR 1 macro
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| /openbmc/linux/drivers/memory/ |
| H A D | Kconfig | 17 config DDR config
|
| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-mb86s7x.c | 31 #define DDR(x) (0x10 + x / 8 * 4) macro
|
| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | processor.hpp | 45 DDR, enumerator
|
| H A D | memory.hpp | 22 DDR, enumerator
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | omap_mmc.h | 95 #define DDR (0x1 << 19) macro
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| /openbmc/u-boot/cmd/ |
| H A D | i2c.c | 1151 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type; in do_sdram() enumerator
|
| /openbmc/linux/drivers/mmc/host/ |
| H A D | omap_hsmmc.c | 97 #define DDR (1 << 19) macro
|
| /openbmc/qemu/target/xtensa/ |
| H A D | cpu.h | 136 DDR = 104, enumerator
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | Processor.v1_20_1.json | 1388 "DDR": "Double data rate synchronous dynamic random-access memory.", string
|
| H A D | Memory.v1_20_0.json | 1265 "DDR": "DDR.", string
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | Processor.v1_20_1.json | 1388 "DDR": "Double data rate synchronous dynamic random-access memory.", string
|
| H A D | Memory.v1_20_0.json | 1265 "DDR": "DDR.", string
|