1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_PRIV_H
7 #define _CORESIGHT_PRIV_H
8
9 #include <linux/amba/bus.h>
10 #include <linux/bitops.h>
11 #include <linux/io.h>
12 #include <linux/coresight.h>
13 #include <linux/pm_runtime.h>
14
15 /*
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
18 * Trace registers in PFTv1.1
19 */
20 #define CORESIGHT_ITCTRL 0xf00
21 #define CORESIGHT_CLAIMSET 0xfa0
22 #define CORESIGHT_CLAIMCLR 0xfa4
23 #define CORESIGHT_LAR 0xfb0
24 #define CORESIGHT_LSR 0xfb4
25 #define CORESIGHT_DEVARCH 0xfbc
26 #define CORESIGHT_AUTHSTATUS 0xfb8
27 #define CORESIGHT_DEVID 0xfc8
28 #define CORESIGHT_DEVTYPE 0xfcc
29
30
31 /*
32 * Coresight device CLAIM protocol.
33 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
34 */
35 #define CORESIGHT_CLAIM_MASK GENMASK(1, 0)
36 #define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
37
38 #define TIMEOUT_US 100
39 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
40
41 #define ETM_MODE_EXCL_KERN BIT(30)
42 #define ETM_MODE_EXCL_USER BIT(31)
43 struct cs_pair_attribute {
44 struct device_attribute attr;
45 u32 lo_off;
46 u32 hi_off;
47 };
48
49 struct cs_off_attribute {
50 struct device_attribute attr;
51 u32 off;
52 };
53
54 extern ssize_t coresight_simple_show32(struct device *_dev,
55 struct device_attribute *attr, char *buf);
56 extern ssize_t coresight_simple_show_pair(struct device *_dev,
57 struct device_attribute *attr, char *buf);
58
59 #define coresight_simple_reg32(name, offset) \
60 (&((struct cs_off_attribute[]) { \
61 { \
62 __ATTR(name, 0444, coresight_simple_show32, NULL), \
63 offset \
64 } \
65 })[0].attr.attr)
66
67 #define coresight_simple_reg64(name, lo_off, hi_off) \
68 (&((struct cs_pair_attribute[]) { \
69 { \
70 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
71 lo_off, hi_off \
72 } \
73 })[0].attr.attr)
74
75 extern const u32 coresight_barrier_pkt[4];
76 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
77
78 enum etm_addr_type {
79 ETM_ADDR_TYPE_NONE,
80 ETM_ADDR_TYPE_SINGLE,
81 ETM_ADDR_TYPE_RANGE,
82 ETM_ADDR_TYPE_START,
83 ETM_ADDR_TYPE_STOP,
84 };
85
86 /**
87 * struct cs_buffer - keep track of a recording session' specifics
88 * @cur: index of the current buffer
89 * @nr_pages: max number of pages granted to us
90 * @pid: PID this cs_buffer belongs to
91 * @offset: offset within the current buffer
92 * @data_size: how much we collected in this run
93 * @snapshot: is this run in snapshot mode
94 * @data_pages: a handle the ring buffer
95 */
96 struct cs_buffers {
97 unsigned int cur;
98 unsigned int nr_pages;
99 pid_t pid;
100 unsigned long offset;
101 local_t data_size;
102 bool snapshot;
103 void **data_pages;
104 };
105
coresight_insert_barrier_packet(void * buf)106 static inline void coresight_insert_barrier_packet(void *buf)
107 {
108 if (buf)
109 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
110 }
111
CS_LOCK(void __iomem * addr)112 static inline void CS_LOCK(void __iomem *addr)
113 {
114 do {
115 /* Wait for things to settle */
116 mb();
117 writel_relaxed(0x0, addr + CORESIGHT_LAR);
118 } while (0);
119 }
120
CS_UNLOCK(void __iomem * addr)121 static inline void CS_UNLOCK(void __iomem *addr)
122 {
123 do {
124 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
125 /* Make sure everyone has seen this */
126 mb();
127 } while (0);
128 }
129
130 void coresight_disable_path(struct list_head *path);
131 int coresight_enable_path(struct list_head *path, enum cs_mode mode,
132 void *sink_data);
133 struct coresight_device *coresight_get_sink(struct list_head *path);
134 struct coresight_device *
135 coresight_get_enabled_sink(struct coresight_device *source);
136 struct coresight_device *coresight_get_sink_by_id(u32 id);
137 struct coresight_device *
138 coresight_find_default_sink(struct coresight_device *csdev);
139 struct list_head *coresight_build_path(struct coresight_device *csdev,
140 struct coresight_device *sink);
141 void coresight_release_path(struct list_head *path);
142 int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
143 void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
144 int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
145 void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
146 int coresight_make_links(struct coresight_device *orig,
147 struct coresight_connection *conn,
148 struct coresight_device *target);
149 void coresight_remove_links(struct coresight_device *orig,
150 struct coresight_connection *conn);
151
152 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
153 extern int etm_readl_cp14(u32 off, unsigned int *val);
154 extern int etm_writel_cp14(u32 off, u32 val);
155 #else
etm_readl_cp14(u32 off,unsigned int * val)156 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
etm_writel_cp14(u32 off,u32 val)157 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
158 #endif
159
160 struct cti_assoc_op {
161 void (*add)(struct coresight_device *csdev);
162 void (*remove)(struct coresight_device *csdev);
163 };
164
165 extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
166 extern void coresight_remove_cti_ops(void);
167
168 /*
169 * Macros and inline functions to handle CoreSight UCI data and driver
170 * private data in AMBA ID table entries, and extract data values.
171 */
172
173 /* coresight AMBA ID, no UCI, no driver data: id table entry */
174 #define CS_AMBA_ID(pid) \
175 { \
176 .id = pid, \
177 .mask = 0x000fffff, \
178 }
179
180 /* coresight AMBA ID, UCI with driver data only: id table entry. */
181 #define CS_AMBA_ID_DATA(pid, dval) \
182 { \
183 .id = pid, \
184 .mask = 0x000fffff, \
185 .data = (void *)&(struct amba_cs_uci_id) \
186 { \
187 .data = (void *)dval, \
188 } \
189 }
190
191 /* coresight AMBA ID, full UCI structure: id table entry. */
192 #define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
193 { \
194 .id = pid, \
195 .mask = m, \
196 .data = (void *)uci_ptr \
197 }
198 #define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
199 /*
200 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
201 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
202 * as a match value for blanket matching all devices in the given CoreSight
203 * device type and architecture.
204 */
205 #define PIDR2_JEDEC BIT(3)
206 #define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
207 /*
208 * Match all PIDs in a given CoreSight device type and architecture, defined
209 * by the uci.
210 */
211 #define CS_AMBA_MATCH_ALL_UCI(uci) \
212 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
213
214 /* extract the data value from a UCI structure given amba_id pointer. */
coresight_get_uci_data(const struct amba_id * id)215 static inline void *coresight_get_uci_data(const struct amba_id *id)
216 {
217 struct amba_cs_uci_id *uci_id = id->data;
218
219 if (!uci_id)
220 return NULL;
221
222 return uci_id->data;
223 }
224
225 void coresight_release_platform_data(struct coresight_device *csdev,
226 struct device *dev,
227 struct coresight_platform_data *pdata);
228 struct coresight_device *
229 coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
230 void coresight_add_helper(struct coresight_device *csdev,
231 struct coresight_device *helper);
232
233 void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
234 struct coresight_device *coresight_get_percpu_sink(int cpu);
235 int coresight_enable_source(struct coresight_device *csdev, enum cs_mode mode,
236 void *data);
237 void coresight_disable_source(struct coresight_device *csdev, void *data);
238
239 #endif
240