1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/property.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/adc/ad_sigma_delta.h>
30
31 /* Registers */
32 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
33 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
34 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
35 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
36 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
37 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
38 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
39 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
40 /* (AD7792)/24-bit (AD7192)) */
41 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
42 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
43
44 /* Communications Register Bit Designations (AD7192_REG_COMM) */
45 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
46 #define AD7192_COMM_WRITE 0 /* Write Operation */
47 #define AD7192_COMM_READ BIT(6) /* Read Operation */
48 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
49 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
50
51 /* Status Register Bit Designations (AD7192_REG_STAT) */
52 #define AD7192_STAT_RDY BIT(7) /* Ready */
53 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
54 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
55 #define AD7192_STAT_PARITY BIT(4) /* Parity */
56 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
57 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
58 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
59
60 /* Mode Register Bit Designations (AD7192_REG_MODE) */
61 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
62 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
63 #define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */
64 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
65 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
66 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
67 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
68 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
69 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
70 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
71 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
72
73 /* Mode Register: AD7192_MODE_SEL options */
74 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
75 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
76 #define AD7192_MODE_IDLE 2 /* Idle Mode */
77 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
78 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
79 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
81 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
82
83 /* Mode Register: AD7192_MODE_CLKSRC options */
84 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
85 /* from MCLK1 to MCLK2 */
86 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
87 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
88 /* available at the MCLK2 pin */
89 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
90 /* at the MCLK2 pin */
91
92 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
93
94 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
95 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
96 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
97 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
98 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
99 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
100 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
101 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
102 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
103 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
104
105 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
106 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
107 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
108 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
109 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
110 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
111 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
112 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
113
114 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
115 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
116 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
117 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
118 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
119 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
120 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
121 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
122 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
123 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
124 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
125 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
126 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
127 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
128 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
129
130 /* ID Register Bit Designations (AD7192_REG_ID) */
131 #define CHIPID_AD7190 0x4
132 #define CHIPID_AD7192 0x0
133 #define CHIPID_AD7193 0x2
134 #define CHIPID_AD7195 0x6
135 #define AD7192_ID_MASK 0x0F
136
137 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
138 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
139 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
140 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
141 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
142 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
143 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
144 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
145
146 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
147 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
148 #define AD7192_INT_FREQ_MHZ 4915200
149
150 #define AD7192_NO_SYNC_FILTER 1
151 #define AD7192_SYNC3_FILTER 3
152 #define AD7192_SYNC4_FILTER 4
153
154 /* NOTE:
155 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
156 * In order to avoid contentions on the SPI bus, it's therefore necessary
157 * to use spi bus locking.
158 *
159 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
160 */
161
162 enum {
163 AD7192_SYSCALIB_ZERO_SCALE,
164 AD7192_SYSCALIB_FULL_SCALE,
165 };
166
167 enum {
168 ID_AD7190,
169 ID_AD7192,
170 ID_AD7193,
171 ID_AD7195,
172 };
173
174 struct ad7192_chip_info {
175 unsigned int chip_id;
176 const char *name;
177 };
178
179 struct ad7192_state {
180 const struct ad7192_chip_info *chip_info;
181 struct regulator *avdd;
182 struct regulator *vref;
183 struct clk *mclk;
184 u16 int_vref_mv;
185 u32 fclk;
186 u32 f_order;
187 u32 mode;
188 u32 conf;
189 u32 scale_avail[8][2];
190 u8 gpocon;
191 u8 clock_sel;
192 struct mutex lock; /* protect sensor state */
193 u8 syscalib_mode[8];
194
195 struct ad_sigma_delta sd;
196 };
197
198 static const char * const ad7192_syscalib_modes[] = {
199 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
200 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
201 };
202
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)203 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
204 const struct iio_chan_spec *chan,
205 unsigned int mode)
206 {
207 struct ad7192_state *st = iio_priv(indio_dev);
208
209 st->syscalib_mode[chan->channel] = mode;
210
211 return 0;
212 }
213
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)214 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
215 const struct iio_chan_spec *chan)
216 {
217 struct ad7192_state *st = iio_priv(indio_dev);
218
219 return st->syscalib_mode[chan->channel];
220 }
221
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)222 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
223 uintptr_t private,
224 const struct iio_chan_spec *chan,
225 const char *buf, size_t len)
226 {
227 struct ad7192_state *st = iio_priv(indio_dev);
228 bool sys_calib;
229 int ret, temp;
230
231 ret = kstrtobool(buf, &sys_calib);
232 if (ret)
233 return ret;
234
235 temp = st->syscalib_mode[chan->channel];
236 if (sys_calib) {
237 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
239 chan->address);
240 else
241 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
242 chan->address);
243 }
244
245 return ret ? ret : len;
246 }
247
248 static const struct iio_enum ad7192_syscalib_mode_enum = {
249 .items = ad7192_syscalib_modes,
250 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
251 .set = ad7192_set_syscalib_mode,
252 .get = ad7192_get_syscalib_mode
253 };
254
255 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
256 {
257 .name = "sys_calibration",
258 .write = ad7192_write_syscalib,
259 .shared = IIO_SEPARATE,
260 },
261 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
262 &ad7192_syscalib_mode_enum),
263 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
264 &ad7192_syscalib_mode_enum),
265 {}
266 };
267
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)268 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
269 {
270 return container_of(sd, struct ad7192_state, sd);
271 }
272
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)273 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
274 {
275 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
276
277 st->conf &= ~AD7192_CONF_CHAN_MASK;
278 st->conf |= AD7192_CONF_CHAN(channel);
279
280 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
281 }
282
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)283 static int ad7192_set_mode(struct ad_sigma_delta *sd,
284 enum ad_sigma_delta_mode mode)
285 {
286 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
287
288 st->mode &= ~AD7192_MODE_SEL_MASK;
289 st->mode |= AD7192_MODE_SEL(mode);
290
291 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
292 }
293
ad7192_append_status(struct ad_sigma_delta * sd,bool append)294 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
295 {
296 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
297 unsigned int mode = st->mode;
298 int ret;
299
300 mode &= ~AD7192_MODE_STA_MASK;
301 mode |= AD7192_MODE_STA(append);
302
303 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
304 if (ret < 0)
305 return ret;
306
307 st->mode = mode;
308
309 return 0;
310 }
311
ad7192_disable_all(struct ad_sigma_delta * sd)312 static int ad7192_disable_all(struct ad_sigma_delta *sd)
313 {
314 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
315 u32 conf = st->conf;
316 int ret;
317
318 conf &= ~AD7192_CONF_CHAN_MASK;
319
320 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
321 if (ret < 0)
322 return ret;
323
324 st->conf = conf;
325
326 return 0;
327 }
328
329 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
330 .set_channel = ad7192_set_channel,
331 .append_status = ad7192_append_status,
332 .disable_all = ad7192_disable_all,
333 .set_mode = ad7192_set_mode,
334 .has_registers = true,
335 .addr_shift = 3,
336 .read_mask = BIT(6),
337 .status_ch_mask = GENMASK(3, 0),
338 .num_slots = 4,
339 .irq_flags = IRQF_TRIGGER_FALLING,
340 };
341
342 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
343 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
344 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
345 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
346 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
347 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
348 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
349 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
350 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
351 };
352
ad7192_calibrate_all(struct ad7192_state * st)353 static int ad7192_calibrate_all(struct ad7192_state *st)
354 {
355 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
356 ARRAY_SIZE(ad7192_calib_arr));
357 }
358
ad7192_valid_external_frequency(u32 freq)359 static inline bool ad7192_valid_external_frequency(u32 freq)
360 {
361 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
362 freq <= AD7192_EXT_FREQ_MHZ_MAX);
363 }
364
ad7192_clock_select(struct ad7192_state * st)365 static int ad7192_clock_select(struct ad7192_state *st)
366 {
367 struct device *dev = &st->sd.spi->dev;
368 unsigned int clock_sel;
369
370 clock_sel = AD7192_CLK_INT;
371
372 /* use internal clock */
373 if (!st->mclk) {
374 if (device_property_read_bool(dev, "adi,int-clock-output-enable"))
375 clock_sel = AD7192_CLK_INT_CO;
376 } else {
377 if (device_property_read_bool(dev, "adi,clock-xtal"))
378 clock_sel = AD7192_CLK_EXT_MCLK1_2;
379 else
380 clock_sel = AD7192_CLK_EXT_MCLK2;
381 }
382
383 return clock_sel;
384 }
385
ad7192_setup(struct iio_dev * indio_dev,struct device * dev)386 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)
387 {
388 struct ad7192_state *st = iio_priv(indio_dev);
389 bool rej60_en, refin2_en;
390 bool buf_en, bipolar, burnout_curr_en;
391 unsigned long long scale_uv;
392 int i, ret, id;
393
394 /* reset the serial interface */
395 ret = ad_sd_reset(&st->sd, 48);
396 if (ret < 0)
397 return ret;
398 usleep_range(500, 1000); /* Wait for at least 500us */
399
400 /* write/read test for device presence */
401 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
402 if (ret)
403 return ret;
404
405 id &= AD7192_ID_MASK;
406
407 if (id != st->chip_info->chip_id)
408 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",
409 id, st->chip_info->chip_id);
410
411 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
412 AD7192_MODE_CLKSRC(st->clock_sel) |
413 AD7192_MODE_RATE(480);
414
415 st->conf = AD7192_CONF_GAIN(0);
416
417 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");
418 if (rej60_en)
419 st->mode |= AD7192_MODE_REJ60;
420
421 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");
422 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
423 st->conf |= AD7192_CONF_REFSEL;
424
425 st->conf &= ~AD7192_CONF_CHOP;
426 st->f_order = AD7192_NO_SYNC_FILTER;
427
428 buf_en = device_property_read_bool(dev, "adi,buffer-enable");
429 if (buf_en)
430 st->conf |= AD7192_CONF_BUF;
431
432 bipolar = device_property_read_bool(dev, "bipolar");
433 if (!bipolar)
434 st->conf |= AD7192_CONF_UNIPOLAR;
435
436 burnout_curr_en = device_property_read_bool(dev,
437 "adi,burnout-currents-enable");
438 if (burnout_curr_en && buf_en) {
439 st->conf |= AD7192_CONF_BURN;
440 } else if (burnout_curr_en) {
441 dev_warn(dev,
442 "Can't enable burnout currents: see CHOP or buffer\n");
443 }
444
445 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
446 if (ret)
447 return ret;
448
449 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
450 if (ret)
451 return ret;
452
453 ret = ad7192_calibrate_all(st);
454 if (ret)
455 return ret;
456
457 /* Populate available ADC input ranges */
458 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
459 scale_uv = ((u64)st->int_vref_mv * 100000000)
460 >> (indio_dev->channels[0].scan_type.realbits -
461 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
462 scale_uv >>= i;
463
464 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
465 st->scale_avail[i][0] = scale_uv;
466 }
467
468 return 0;
469 }
470
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)471 static ssize_t ad7192_show_ac_excitation(struct device *dev,
472 struct device_attribute *attr,
473 char *buf)
474 {
475 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
476 struct ad7192_state *st = iio_priv(indio_dev);
477
478 return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX));
479 }
480
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)481 static ssize_t ad7192_show_bridge_switch(struct device *dev,
482 struct device_attribute *attr,
483 char *buf)
484 {
485 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
486 struct ad7192_state *st = iio_priv(indio_dev);
487
488 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
489 }
490
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)491 static ssize_t ad7192_set(struct device *dev,
492 struct device_attribute *attr,
493 const char *buf,
494 size_t len)
495 {
496 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
497 struct ad7192_state *st = iio_priv(indio_dev);
498 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
499 int ret;
500 bool val;
501
502 ret = kstrtobool(buf, &val);
503 if (ret < 0)
504 return ret;
505
506 ret = iio_device_claim_direct_mode(indio_dev);
507 if (ret)
508 return ret;
509
510 switch ((u32)this_attr->address) {
511 case AD7192_REG_GPOCON:
512 if (val)
513 st->gpocon |= AD7192_GPOCON_BPDSW;
514 else
515 st->gpocon &= ~AD7192_GPOCON_BPDSW;
516
517 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
518 break;
519 case AD7192_REG_CONF:
520 if (val)
521 st->conf |= AD7192_CONF_ACX;
522 else
523 st->conf &= ~AD7192_CONF_ACX;
524
525 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
526 break;
527 default:
528 ret = -EINVAL;
529 }
530
531 iio_device_release_direct_mode(indio_dev);
532
533 return ret ? ret : len;
534 }
535
ad7192_get_available_filter_freq(struct ad7192_state * st,int * freq)536 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
537 int *freq)
538 {
539 unsigned int fadc;
540
541 /* Formulas for filter at page 25 of the datasheet */
542 fadc = DIV_ROUND_CLOSEST(st->fclk,
543 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
544 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
545
546 fadc = DIV_ROUND_CLOSEST(st->fclk,
547 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
548 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
549
550 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
551 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
552 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
553 }
554
ad7192_show_filter_avail(struct device * dev,struct device_attribute * attr,char * buf)555 static ssize_t ad7192_show_filter_avail(struct device *dev,
556 struct device_attribute *attr,
557 char *buf)
558 {
559 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
560 struct ad7192_state *st = iio_priv(indio_dev);
561 unsigned int freq_avail[4], i;
562 size_t len = 0;
563
564 ad7192_get_available_filter_freq(st, freq_avail);
565
566 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
567 len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000,
568 freq_avail[i] % 1000);
569
570 buf[len - 1] = '\n';
571
572 return len;
573 }
574
575 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
576 0444, ad7192_show_filter_avail, NULL, 0);
577
578 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
579 ad7192_show_bridge_switch, ad7192_set,
580 AD7192_REG_GPOCON);
581
582 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
583 ad7192_show_ac_excitation, ad7192_set,
584 AD7192_REG_CONF);
585
586 static struct attribute *ad7192_attributes[] = {
587 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
588 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
589 NULL
590 };
591
592 static const struct attribute_group ad7192_attribute_group = {
593 .attrs = ad7192_attributes,
594 };
595
596 static struct attribute *ad7195_attributes[] = {
597 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
598 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
599 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
600 NULL
601 };
602
603 static const struct attribute_group ad7195_attribute_group = {
604 .attrs = ad7195_attributes,
605 };
606
ad7192_get_temp_scale(bool unipolar)607 static unsigned int ad7192_get_temp_scale(bool unipolar)
608 {
609 return unipolar ? 2815 * 2 : 2815;
610 }
611
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)612 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
613 int val, int val2)
614 {
615 int freq_avail[4], i, ret, freq;
616 unsigned int diff_new, diff_old;
617 int idx = 0;
618
619 diff_old = U32_MAX;
620 freq = val * 1000 + val2;
621
622 ad7192_get_available_filter_freq(st, freq_avail);
623
624 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
625 diff_new = abs(freq - freq_avail[i]);
626 if (diff_new < diff_old) {
627 diff_old = diff_new;
628 idx = i;
629 }
630 }
631
632 switch (idx) {
633 case 0:
634 st->f_order = AD7192_SYNC4_FILTER;
635 st->mode &= ~AD7192_MODE_SINC3;
636
637 st->conf |= AD7192_CONF_CHOP;
638 break;
639 case 1:
640 st->f_order = AD7192_SYNC3_FILTER;
641 st->mode |= AD7192_MODE_SINC3;
642
643 st->conf |= AD7192_CONF_CHOP;
644 break;
645 case 2:
646 st->f_order = AD7192_NO_SYNC_FILTER;
647 st->mode &= ~AD7192_MODE_SINC3;
648
649 st->conf &= ~AD7192_CONF_CHOP;
650 break;
651 case 3:
652 st->f_order = AD7192_NO_SYNC_FILTER;
653 st->mode |= AD7192_MODE_SINC3;
654
655 st->conf &= ~AD7192_CONF_CHOP;
656 break;
657 }
658
659 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
660 if (ret < 0)
661 return ret;
662
663 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
664 }
665
ad7192_get_3db_filter_freq(struct ad7192_state * st)666 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
667 {
668 unsigned int fadc;
669
670 fadc = DIV_ROUND_CLOSEST(st->fclk,
671 st->f_order * AD7192_MODE_RATE(st->mode));
672
673 if (st->conf & AD7192_CONF_CHOP)
674 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
675 if (st->mode & AD7192_MODE_SINC3)
676 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
677 else
678 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
679 }
680
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)681 static int ad7192_read_raw(struct iio_dev *indio_dev,
682 struct iio_chan_spec const *chan,
683 int *val,
684 int *val2,
685 long m)
686 {
687 struct ad7192_state *st = iio_priv(indio_dev);
688 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
689
690 switch (m) {
691 case IIO_CHAN_INFO_RAW:
692 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
693 case IIO_CHAN_INFO_SCALE:
694 switch (chan->type) {
695 case IIO_VOLTAGE:
696 mutex_lock(&st->lock);
697 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
698 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
699 mutex_unlock(&st->lock);
700 return IIO_VAL_INT_PLUS_NANO;
701 case IIO_TEMP:
702 *val = 0;
703 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
704 return IIO_VAL_INT_PLUS_NANO;
705 default:
706 return -EINVAL;
707 }
708 case IIO_CHAN_INFO_OFFSET:
709 if (!unipolar)
710 *val = -(1 << (chan->scan_type.realbits - 1));
711 else
712 *val = 0;
713 /* Kelvin to Celsius */
714 if (chan->type == IIO_TEMP)
715 *val -= 273 * ad7192_get_temp_scale(unipolar);
716 return IIO_VAL_INT;
717 case IIO_CHAN_INFO_SAMP_FREQ:
718 *val = st->fclk /
719 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
720 return IIO_VAL_INT;
721 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
722 *val = ad7192_get_3db_filter_freq(st);
723 *val2 = 1000;
724 return IIO_VAL_FRACTIONAL;
725 }
726
727 return -EINVAL;
728 }
729
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)730 static int ad7192_write_raw(struct iio_dev *indio_dev,
731 struct iio_chan_spec const *chan,
732 int val,
733 int val2,
734 long mask)
735 {
736 struct ad7192_state *st = iio_priv(indio_dev);
737 int ret, i, div;
738 unsigned int tmp;
739
740 ret = iio_device_claim_direct_mode(indio_dev);
741 if (ret)
742 return ret;
743
744 switch (mask) {
745 case IIO_CHAN_INFO_SCALE:
746 ret = -EINVAL;
747 mutex_lock(&st->lock);
748 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
749 if (val2 == st->scale_avail[i][1]) {
750 ret = 0;
751 tmp = st->conf;
752 st->conf &= ~AD7192_CONF_GAIN(-1);
753 st->conf |= AD7192_CONF_GAIN(i);
754 if (tmp == st->conf)
755 break;
756 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
757 3, st->conf);
758 ad7192_calibrate_all(st);
759 break;
760 }
761 mutex_unlock(&st->lock);
762 break;
763 case IIO_CHAN_INFO_SAMP_FREQ:
764 if (!val) {
765 ret = -EINVAL;
766 break;
767 }
768
769 div = st->fclk / (val * st->f_order * 1024);
770 if (div < 1 || div > 1023) {
771 ret = -EINVAL;
772 break;
773 }
774
775 st->mode &= ~AD7192_MODE_RATE(-1);
776 st->mode |= AD7192_MODE_RATE(div);
777 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
778 break;
779 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
780 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
781 break;
782 default:
783 ret = -EINVAL;
784 }
785
786 iio_device_release_direct_mode(indio_dev);
787
788 return ret;
789 }
790
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)791 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
792 struct iio_chan_spec const *chan,
793 long mask)
794 {
795 switch (mask) {
796 case IIO_CHAN_INFO_SCALE:
797 return IIO_VAL_INT_PLUS_NANO;
798 case IIO_CHAN_INFO_SAMP_FREQ:
799 return IIO_VAL_INT;
800 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
801 return IIO_VAL_INT_PLUS_MICRO;
802 default:
803 return -EINVAL;
804 }
805 }
806
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)807 static int ad7192_read_avail(struct iio_dev *indio_dev,
808 struct iio_chan_spec const *chan,
809 const int **vals, int *type, int *length,
810 long mask)
811 {
812 struct ad7192_state *st = iio_priv(indio_dev);
813
814 switch (mask) {
815 case IIO_CHAN_INFO_SCALE:
816 *vals = (int *)st->scale_avail;
817 *type = IIO_VAL_INT_PLUS_NANO;
818 /* Values are stored in a 2D matrix */
819 *length = ARRAY_SIZE(st->scale_avail) * 2;
820
821 return IIO_AVAIL_LIST;
822 }
823
824 return -EINVAL;
825 }
826
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)827 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
828 {
829 struct ad7192_state *st = iio_priv(indio_dev);
830 u32 conf = st->conf;
831 int ret;
832 int i;
833
834 conf &= ~AD7192_CONF_CHAN_MASK;
835 for_each_set_bit(i, scan_mask, 8)
836 conf |= AD7192_CONF_CHAN(i);
837
838 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
839 if (ret < 0)
840 return ret;
841
842 st->conf = conf;
843
844 return 0;
845 }
846
847 static const struct iio_info ad7192_info = {
848 .read_raw = ad7192_read_raw,
849 .write_raw = ad7192_write_raw,
850 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
851 .read_avail = ad7192_read_avail,
852 .attrs = &ad7192_attribute_group,
853 .validate_trigger = ad_sd_validate_trigger,
854 .update_scan_mode = ad7192_update_scan_mode,
855 };
856
857 static const struct iio_info ad7195_info = {
858 .read_raw = ad7192_read_raw,
859 .write_raw = ad7192_write_raw,
860 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
861 .read_avail = ad7192_read_avail,
862 .attrs = &ad7195_attribute_group,
863 .validate_trigger = ad_sd_validate_trigger,
864 .update_scan_mode = ad7192_update_scan_mode,
865 };
866
867 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
868 _type, _mask_type_av, _ext_info) \
869 { \
870 .type = (_type), \
871 .differential = ((_channel2) == -1 ? 0 : 1), \
872 .indexed = 1, \
873 .channel = (_channel1), \
874 .channel2 = (_channel2), \
875 .address = (_address), \
876 .extend_name = (_extend_name), \
877 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
878 BIT(IIO_CHAN_INFO_OFFSET), \
879 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
880 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
881 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
882 .info_mask_shared_by_type_available = (_mask_type_av), \
883 .ext_info = (_ext_info), \
884 .scan_index = (_si), \
885 .scan_type = { \
886 .sign = 'u', \
887 .realbits = 24, \
888 .storagebits = 32, \
889 .endianness = IIO_BE, \
890 }, \
891 }
892
893 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
894 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
895 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
896 ad7192_calibsys_ext_info)
897
898 #define AD719x_CHANNEL(_si, _channel1, _address) \
899 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
900 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
901
902 #define AD719x_TEMP_CHANNEL(_si, _address) \
903 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
904
905 static const struct iio_chan_spec ad7192_channels[] = {
906 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
907 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
908 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
909 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
910 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
911 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
912 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
913 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
914 IIO_CHAN_SOFT_TIMESTAMP(8),
915 };
916
917 static const struct iio_chan_spec ad7193_channels[] = {
918 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
919 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
920 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
921 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
922 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
923 AD719x_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
924 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
925 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
926 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
927 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
928 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
929 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
930 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
931 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
932 IIO_CHAN_SOFT_TIMESTAMP(14),
933 };
934
935 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
936 [ID_AD7190] = {
937 .chip_id = CHIPID_AD7190,
938 .name = "ad7190",
939 },
940 [ID_AD7192] = {
941 .chip_id = CHIPID_AD7192,
942 .name = "ad7192",
943 },
944 [ID_AD7193] = {
945 .chip_id = CHIPID_AD7193,
946 .name = "ad7193",
947 },
948 [ID_AD7195] = {
949 .chip_id = CHIPID_AD7195,
950 .name = "ad7195",
951 },
952 };
953
ad7192_channels_config(struct iio_dev * indio_dev)954 static int ad7192_channels_config(struct iio_dev *indio_dev)
955 {
956 struct ad7192_state *st = iio_priv(indio_dev);
957
958 switch (st->chip_info->chip_id) {
959 case CHIPID_AD7193:
960 indio_dev->channels = ad7193_channels;
961 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
962 break;
963 default:
964 indio_dev->channels = ad7192_channels;
965 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
966 break;
967 }
968
969 return 0;
970 }
971
ad7192_reg_disable(void * reg)972 static void ad7192_reg_disable(void *reg)
973 {
974 regulator_disable(reg);
975 }
976
ad7192_probe(struct spi_device * spi)977 static int ad7192_probe(struct spi_device *spi)
978 {
979 struct ad7192_state *st;
980 struct iio_dev *indio_dev;
981 int ret;
982
983 if (!spi->irq) {
984 dev_err(&spi->dev, "no IRQ?\n");
985 return -ENODEV;
986 }
987
988 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
989 if (!indio_dev)
990 return -ENOMEM;
991
992 st = iio_priv(indio_dev);
993
994 mutex_init(&st->lock);
995
996 st->avdd = devm_regulator_get(&spi->dev, "avdd");
997 if (IS_ERR(st->avdd))
998 return PTR_ERR(st->avdd);
999
1000 ret = regulator_enable(st->avdd);
1001 if (ret) {
1002 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
1003 return ret;
1004 }
1005
1006 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
1007 if (ret)
1008 return ret;
1009
1010 ret = devm_regulator_get_enable(&spi->dev, "dvdd");
1011 if (ret)
1012 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n");
1013
1014 st->vref = devm_regulator_get_optional(&spi->dev, "vref");
1015 if (IS_ERR(st->vref)) {
1016 if (PTR_ERR(st->vref) != -ENODEV)
1017 return PTR_ERR(st->vref);
1018
1019 ret = regulator_get_voltage(st->avdd);
1020 if (ret < 0)
1021 return dev_err_probe(&spi->dev, ret,
1022 "Device tree error, AVdd voltage undefined\n");
1023 } else {
1024 ret = regulator_enable(st->vref);
1025 if (ret) {
1026 dev_err(&spi->dev, "Failed to enable specified Vref supply\n");
1027 return ret;
1028 }
1029
1030 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref);
1031 if (ret)
1032 return ret;
1033
1034 ret = regulator_get_voltage(st->vref);
1035 if (ret < 0)
1036 return dev_err_probe(&spi->dev, ret,
1037 "Device tree error, Vref voltage undefined\n");
1038 }
1039 st->int_vref_mv = ret / 1000;
1040
1041 st->chip_info = spi_get_device_match_data(spi);
1042 if (!st->chip_info)
1043 return -ENODEV;
1044
1045 indio_dev->name = st->chip_info->name;
1046 indio_dev->modes = INDIO_DIRECT_MODE;
1047
1048 ret = ad7192_channels_config(indio_dev);
1049 if (ret < 0)
1050 return ret;
1051
1052 if (st->chip_info->chip_id == CHIPID_AD7195)
1053 indio_dev->info = &ad7195_info;
1054 else
1055 indio_dev->info = &ad7192_info;
1056
1057 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
1058 if (ret)
1059 return ret;
1060
1061 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1062 if (ret)
1063 return ret;
1064
1065 st->fclk = AD7192_INT_FREQ_MHZ;
1066
1067 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk");
1068 if (IS_ERR(st->mclk))
1069 return PTR_ERR(st->mclk);
1070
1071 st->clock_sel = ad7192_clock_select(st);
1072
1073 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1074 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1075 st->fclk = clk_get_rate(st->mclk);
1076 if (!ad7192_valid_external_frequency(st->fclk)) {
1077 dev_err(&spi->dev,
1078 "External clock frequency out of bounds\n");
1079 return -EINVAL;
1080 }
1081 }
1082
1083 ret = ad7192_setup(indio_dev, &spi->dev);
1084 if (ret)
1085 return ret;
1086
1087 return devm_iio_device_register(&spi->dev, indio_dev);
1088 }
1089
1090 static const struct of_device_id ad7192_of_match[] = {
1091 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1092 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1093 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1094 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1095 {}
1096 };
1097 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1098
1099 static const struct spi_device_id ad7192_ids[] = {
1100 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1101 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1102 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1103 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1104 {}
1105 };
1106 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1107
1108 static struct spi_driver ad7192_driver = {
1109 .driver = {
1110 .name = "ad7192",
1111 .of_match_table = ad7192_of_match,
1112 },
1113 .probe = ad7192_probe,
1114 .id_table = ad7192_ids,
1115 };
1116 module_spi_driver(ad7192_driver);
1117
1118 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1119 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1120 MODULE_LICENSE("GPL v2");
1121 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1122