xref: /openbmc/linux/drivers/net/ethernet/cirrus/cs89x0.h (revision cbecf716ca618fd44feda6bd9a64a8179d031fc5)
1  /*  Copyright, 1988-1992, Russell Nelson, Crynwr Software
2  
3     This program is free software; you can redistribute it and/or modify
4     it under the terms of the GNU General Public License as published by
5     the Free Software Foundation, version 1.
6  
7     This program is distributed in the hope that it will be useful,
8     but WITHOUT ANY WARRANTY; without even the implied warranty of
9     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10     GNU General Public License for more details.
11  
12     You should have received a copy of the GNU General Public License
13     along with this program; if not, write to the Free Software
14     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15     */
16  
17  
18  #define PP_ChipID 0x0000	/* offset   0h -> Corp -ID              */
19  				/* offset   2h -> Model/Product Number  */
20  				/* offset   3h -> Chip Revision Number  */
21  
22  #define PP_ISAIOB 0x0020	/*  IO base address */
23  #define PP_CS8900_ISAINT 0x0022	/*  ISA interrupt select */
24  #define PP_CS8920_ISAINT 0x0370	/*  ISA interrupt select */
25  #define PP_CS8900_ISADMA 0x0024	/*  ISA Rec DMA channel */
26  #define PP_CS8920_ISADMA 0x0374	/*  ISA Rec DMA channel */
27  #define PP_ISASOF 0x0026	/*  ISA DMA offset */
28  #define PP_DmaFrameCnt 0x0028	/*  ISA DMA Frame count */
29  #define PP_DmaByteCnt 0x002A	/*  ISA DMA Byte count */
30  #define PP_CS8900_ISAMemB 0x002C	/*  Memory base */
31  #define PP_CS8920_ISAMemB 0x0348 /*  */
32  
33  #define PP_ISABootBase 0x0030	/*  Boot Prom base  */
34  #define PP_ISABootMask 0x0034	/*  Boot Prom Mask */
35  
36  /* EEPROM data and command registers */
37  #define PP_EECMD 0x0040		/*  NVR Interface Command register */
38  #define PP_EEData 0x0042	/*  NVR Interface Data Register */
39  #define PP_DebugReg 0x0044	/*  Debug Register */
40  
41  #define PP_RxCFG 0x0102		/*  Rx Bus config */
42  #define PP_RxCTL 0x0104		/*  Receive Control Register */
43  #define PP_TxCFG 0x0106		/*  Transmit Config Register */
44  #define PP_TxCMD 0x0108		/*  Transmit Command Register */
45  #define PP_BufCFG 0x010A	/*  Bus configuration Register */
46  #define PP_LineCTL 0x0112	/*  Line Config Register */
47  #define PP_SelfCTL 0x0114	/*  Self Command Register */
48  #define PP_BusCTL 0x0116	/*  ISA bus control Register */
49  #define PP_TestCTL 0x0118	/*  Test Register */
50  #define PP_AutoNegCTL 0x011C	/*  Auto Negotiation Ctrl */
51  
52  #define PP_ISQ 0x0120		/*  Interrupt Status */
53  #define PP_RxEvent 0x0124	/*  Rx Event Register */
54  #define PP_TxEvent 0x0128	/*  Tx Event Register */
55  #define PP_BufEvent 0x012C	/*  Bus Event Register */
56  #define PP_RxMiss 0x0130	/*  Receive Miss Count */
57  #define PP_TxCol 0x0132		/*  Transmit Collision Count */
58  #define PP_LineST 0x0134	/*  Line State Register */
59  #define PP_SelfST 0x0136	/*  Self State register */
60  #define PP_BusST 0x0138		/*  Bus Status */
61  #define PP_TDR 0x013C		/*  Time Domain Reflectometry */
62  #define PP_AutoNegST 0x013E	/*  Auto Neg Status */
63  #define PP_TxCommand 0x0144	/*  Tx Command */
64  #define PP_TxLength 0x0146	/*  Tx Length */
65  #define PP_LAF 0x0150		/*  Hash Table */
66  #define PP_IA 0x0158		/*  Physical Address Register */
67  
68  #define PP_RxStatus 0x0400	/*  Receive start of frame */
69  #define PP_RxLength 0x0402	/*  Receive Length of frame */
70  #define PP_RxFrame 0x0404	/*  Receive frame pointer */
71  #define PP_TxFrame 0x0A00	/*  Transmit frame pointer */
72  
73  /*  Primary I/O Base Address. If no I/O base is supplied by the user, then this */
74  /*  can be used as the default I/O base to access the PacketPage Area. */
75  #define DEFAULTIOBASE 0x0300
76  #define FIRST_IO 0x020C		/*  First I/O port to check */
77  #define LAST_IO 0x037C		/*  Last I/O port to check (+10h) */
78  #define ADD_MASK 0x3000		/*  Mask it use of the ADD_PORT register */
79  #define ADD_SIG 0x3000		/*  Expected ID signature */
80  
81  /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
82  #ifdef CONFIG_MAC
83  #define LCSLOTBASE 0xfee00000
84  #define MMIOBASE 0x40000
85  #endif
86  
87  #define CHIP_EISA_ID_SIG 0x630E   /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
88  #define CHIP_EISA_ID_SIG_STR "0x630E"
89  
90  #ifdef IBMEIPKT
91  #define EISA_ID_SIG 0x4D24	/*  IBM */
92  #define PART_NO_SIG 0x1010	/*  IBM */
93  #define MONGOOSE_BIT 0x0000	/*  IBM */
94  #else
95  #define EISA_ID_SIG 0x630E	/*  PnP Vendor ID (same as chip id for Crystal board) */
96  #define PART_NO_SIG 0x4000	/*  ID code CS8920 board (PnP Vendor Product code) */
97  #define MONGOOSE_BIT 0x2000	/*  PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
98  #endif
99  
100  #define PRODUCT_ID_ADD 0x0002   /*  Address of product ID */
101  
102  /*  Mask to find out the types of  registers */
103  #define REG_TYPE_MASK 0x001F
104  
105  /*  Eeprom Commands */
106  #define ERSE_WR_ENBL 0x00F0
107  #define ERSE_WR_DISABLE 0x0000
108  
109  /*  Defines Control/Config register quintuplet numbers */
110  #define RX_BUF_CFG 0x0003
111  #define RX_CONTROL 0x0005
112  #define TX_CFG 0x0007
113  #define TX_COMMAND 0x0009
114  #define BUF_CFG 0x000B
115  #define LINE_CONTROL 0x0013
116  #define SELF_CONTROL 0x0015
117  #define BUS_CONTROL 0x0017
118  #define TEST_CONTROL 0x0019
119  
120  /*  Defines Status/Count registers quintuplet numbers */
121  #define RX_EVENT 0x0004
122  #define TX_EVENT 0x0008
123  #define BUF_EVENT 0x000C
124  #define RX_MISS_COUNT 0x0010
125  #define TX_COL_COUNT 0x0012
126  #define LINE_STATUS 0x0014
127  #define SELF_STATUS 0x0016
128  #define BUS_STATUS 0x0018
129  #define TDR 0x001C
130  
131  /* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
132  #define SKIP_1 0x0040
133  #define RX_STREAM_ENBL 0x0080
134  #define RX_OK_ENBL 0x0100
135  #define RX_DMA_ONLY 0x0200
136  #define AUTO_RX_DMA 0x0400
137  #define BUFFER_CRC 0x0800
138  #define RX_CRC_ERROR_ENBL 0x1000
139  #define RX_RUNT_ENBL 0x2000
140  #define RX_EXTRA_DATA_ENBL 0x4000
141  
142  /* PP_RxCTL - Receive Control bit definition - Read/write */
143  #define RX_IA_HASH_ACCEPT 0x0040
144  #define RX_PROM_ACCEPT 0x0080
145  #define RX_OK_ACCEPT 0x0100
146  #define RX_MULTCAST_ACCEPT 0x0200
147  #define RX_IA_ACCEPT 0x0400
148  #define RX_BROADCAST_ACCEPT 0x0800
149  #define RX_BAD_CRC_ACCEPT 0x1000
150  #define RX_RUNT_ACCEPT 0x2000
151  #define RX_EXTRA_DATA_ACCEPT 0x4000
152  #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
153  /*  Default receive mode - individually addressed, broadcast, and error free */
154  #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
155  
156  /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
157  #define TX_LOST_CRS_ENBL 0x0040
158  #define TX_SQE_ERROR_ENBL 0x0080
159  #define TX_OK_ENBL 0x0100
160  #define TX_LATE_COL_ENBL 0x0200
161  #define TX_JBR_ENBL 0x0400
162  #define TX_ANY_COL_ENBL 0x0800
163  #define TX_16_COL_ENBL 0x8000
164  
165  /* PP_TxCMD - Transmit Command bit definition - Read-only */
166  #define TX_START_4_BYTES 0x0000
167  #define TX_START_64_BYTES 0x0040
168  #define TX_START_128_BYTES 0x0080
169  #define TX_START_ALL_BYTES 0x00C0
170  #define TX_FORCE 0x0100
171  #define TX_ONE_COL 0x0200
172  #define TX_TWO_PART_DEFF_DISABLE 0x0400
173  #define TX_NO_CRC 0x1000
174  #define TX_RUNT 0x2000
175  
176  /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
177  #define GENERATE_SW_INTERRUPT 0x0040
178  #define RX_DMA_ENBL 0x0080
179  #define READY_FOR_TX_ENBL 0x0100
180  #define TX_UNDERRUN_ENBL 0x0200
181  #define RX_MISS_ENBL 0x0400
182  #define RX_128_BYTE_ENBL 0x0800
183  #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
184  #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
185  #define RX_DEST_MATCH_ENBL 0x8000
186  
187  /* PP_LineCTL - Line Control bit definition - Read/write */
188  #define SERIAL_RX_ON 0x0040
189  #define SERIAL_TX_ON 0x0080
190  #define AUI_ONLY 0x0100
191  #define AUTO_AUI_10BASET 0x0200
192  #define MODIFIED_BACKOFF 0x0800
193  #define NO_AUTO_POLARITY 0x1000
194  #define TWO_PART_DEFDIS 0x2000
195  #define LOW_RX_SQUELCH 0x4000
196  
197  /* PP_SelfCTL - Software Self Control bit definition - Read/write */
198  #define POWER_ON_RESET 0x0040
199  #define SW_STOP 0x0100
200  #define SLEEP_ON 0x0200
201  #define AUTO_WAKEUP 0x0400
202  #define HCB0_ENBL 0x1000
203  #define HCB1_ENBL 0x2000
204  #define HCB0 0x4000
205  #define HCB1 0x8000
206  
207  /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
208  #define RESET_RX_DMA 0x0040
209  #define MEMORY_ON 0x0400
210  #define DMA_BURST_MODE 0x0800
211  #define IO_CHANNEL_READY_ON 0x1000
212  #define RX_DMA_SIZE_64K 0x2000
213  #define ENABLE_IRQ 0x8000
214  
215  /* PP_TestCTL - Test Control bit definition - Read/write */
216  #define LINK_OFF 0x0080
217  #define ENDEC_LOOPBACK 0x0200
218  #define AUI_LOOPBACK 0x0400
219  #define BACKOFF_OFF 0x0800
220  #define FDX_8900 0x4000
221  #define FAST_TEST 0x8000
222  
223  /* PP_RxEvent - Receive Event Bit definition - Read-only */
224  #define RX_IA_HASHED 0x0040
225  #define RX_DRIBBLE 0x0080
226  #define RX_OK 0x0100
227  #define RX_HASHED 0x0200
228  #define RX_IA 0x0400
229  #define RX_BROADCAST 0x0800
230  #define RX_CRC_ERROR 0x1000
231  #define RX_RUNT 0x2000
232  #define RX_EXTRA_DATA 0x4000
233  
234  #define HASH_INDEX_MASK 0x0FC00
235  
236  /* PP_TxEvent - Transmit Event Bit definition - Read-only */
237  #define TX_LOST_CRS 0x0040
238  #define TX_SQE_ERROR 0x0080
239  #define TX_OK 0x0100
240  #define TX_LATE_COL 0x0200
241  #define TX_JBR 0x0400
242  #define TX_16_COL 0x8000
243  #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
244  #define TX_COL_COUNT_MASK 0x7800
245  
246  /* PP_BufEvent - Buffer Event Bit definition - Read-only */
247  #define SW_INTERRUPT 0x0040
248  #define RX_DMA 0x0080
249  #define READY_FOR_TX 0x0100
250  #define TX_UNDERRUN 0x0200
251  #define RX_MISS 0x0400
252  #define RX_128_BYTE 0x0800
253  #define TX_COL_OVRFLW 0x1000
254  #define RX_MISS_OVRFLW 0x2000
255  #define RX_DEST_MATCH 0x8000
256  
257  /* PP_LineST - Ethernet Line Status bit definition - Read-only */
258  #define LINK_OK 0x0080
259  #define AUI_ON 0x0100
260  #define TENBASET_ON 0x0200
261  #define POLARITY_OK 0x1000
262  #define CRS_OK 0x4000
263  
264  /* PP_SelfST - Chip Software Status bit definition */
265  #define ACTIVE_33V 0x0040
266  #define INIT_DONE 0x0080
267  #define SI_BUSY 0x0100
268  #define EEPROM_PRESENT 0x0200
269  #define EEPROM_OK 0x0400
270  #define EL_PRESENT 0x0800
271  #define EE_SIZE_64 0x1000
272  
273  /* PP_BusST - ISA Bus Status bit definition */
274  #define TX_BID_ERROR 0x0080
275  #define READY_FOR_TX_NOW 0x0100
276  
277  /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
278  #define RE_NEG_NOW 0x0040
279  #define ALLOW_FDX 0x0080
280  #define AUTO_NEG_ENABLE 0x0100
281  #define NLP_ENABLE 0x0200
282  #define FORCE_FDX 0x8000
283  #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
284  #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
285  
286  /* PP_AutoNegST - Auto Negotiation Status bit definition */
287  #define AUTO_NEG_BUSY 0x0080
288  #define FLP_LINK 0x0100
289  #define FLP_LINK_GOOD 0x0800
290  #define LINK_FAULT 0x1000
291  #define HDX_ACTIVE 0x4000
292  #define FDX_ACTIVE 0x8000
293  
294  /*  The following block defines the ISQ event types */
295  #define ISQ_RECEIVER_EVENT 0x04
296  #define ISQ_TRANSMITTER_EVENT 0x08
297  #define ISQ_BUFFER_EVENT 0x0c
298  #define ISQ_RX_MISS_EVENT 0x10
299  #define ISQ_TX_COL_EVENT 0x12
300  
301  #define ISQ_EVENT_MASK 0x003F   /*  ISQ mask to find out type of event */
302  #define ISQ_HIST 16		/*  small history buffer */
303  #define AUTOINCREMENT 0x8000	/*  Bit mask to set bit-15 for autoincrement */
304  
305  #define TXRXBUFSIZE 0x0600
306  #define RXDMABUFSIZE 0x8000
307  #define RXDMASIZE 0x4000
308  #define TXRX_LENGTH_MASK 0x07FF
309  
310  /*  rx options bits */
311  #define RCV_WITH_RXON	1       /*  Set SerRx ON */
312  #define RCV_COUNTS	2       /*  Use Framecnt1 */
313  #define RCV_PONG	4       /*  Pong respondent */
314  #define RCV_DONG	8       /*  Dong operation */
315  #define RCV_POLLING	0x10	/*  Poll RxEvent */
316  #define RCV_ISQ		0x20	/*  Use ISQ, int */
317  #define RCV_AUTO_DMA	0x100	/*  Set AutoRxDMAE */
318  #define RCV_DMA		0x200	/*  Set RxDMA only */
319  #define RCV_DMA_ALL	0x400	/*  Copy all DMA'ed */
320  #define RCV_FIXED_DATA	0x800	/*  Every frame same */
321  #define RCV_IO		0x1000	/*  Use ISA IO only */
322  #define RCV_MEMORY	0x2000	/*  Use ISA Memory */
323  
324  #define RAM_SIZE	0x1000       /*  The card has 4k bytes or RAM */
325  #define PKT_START PP_TxFrame  /*  Start of packet RAM */
326  
327  #define RX_FRAME_PORT	0x0000
328  #define TX_FRAME_PORT RX_FRAME_PORT
329  #define TX_CMD_PORT	0x0004
330  #define TX_NOW		0x0000       /*  Tx packet after   5 bytes copied */
331  #define TX_AFTER_381	0x0040       /*  Tx packet after 381 bytes copied */
332  #define TX_AFTER_ALL	0x00c0       /*  Tx packet after all bytes copied */
333  #define TX_LEN_PORT	0x0006
334  #define ISQ_PORT	0x0008
335  #define ADD_PORT	0x000A
336  #define DATA_PORT	0x000C
337  
338  #define EEPROM_WRITE_EN		0x00F0
339  #define EEPROM_WRITE_DIS	0x0000
340  #define EEPROM_WRITE_CMD	0x0100
341  #define EEPROM_READ_CMD		0x0200
342  
343  /*  Receive Header */
344  /*  Description of header of each packet in receive area of memory */
345  #define RBUF_EVENT_LOW	0   /*  Low byte of RxEvent - status of received frame */
346  #define RBUF_EVENT_HIGH	1   /*  High byte of RxEvent - status of received frame */
347  #define RBUF_LEN_LOW	2   /*  Length of received data - low byte */
348  #define RBUF_LEN_HI	3   /*  Length of received data - high byte */
349  #define RBUF_HEAD_LEN	4   /*  Length of this header */
350  
351  #define CHIP_READ 0x1   /*  Used to mark state of the repins code (chip or dma) */
352  #define DMA_READ 0x2   /*  Used to mark state of the repins code (chip or dma) */
353  
354  /*  for bios scan */
355  /*  */
356  #ifdef CSDEBUG
357  /*  use these values for debugging bios scan */
358  #define BIOS_START_SEG 0x00000
359  #define BIOS_OFFSET_INC 0x0010
360  #else
361  #define BIOS_START_SEG 0x0c000
362  #define BIOS_OFFSET_INC 0x0200
363  #endif
364  
365  #define BIOS_LAST_OFFSET 0x0fc00
366  
367  /*  Byte offsets into the EEPROM configuration buffer */
368  #define ISA_CNF_OFFSET 0x6
369  #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8)			/*  8900 eeprom */
370  #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8)		/*  8920 eeprom */
371  
372    /*  the assumption here is that the bits in the eeprom are generally  */
373    /*  in the same position as those in the autonegctl register. */
374    /*  Of course the IMM bit is not in that register so it must be  */
375    /*  masked out */
376  #define EE_FORCE_FDX  0x8000
377  #define EE_NLP_ENABLE 0x0200
378  #define EE_AUTO_NEG_ENABLE 0x0100
379  #define EE_ALLOW_FDX 0x0080
380  #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
381  
382  #define IMM_BIT 0x0040		/*  ignore missing media	 */
383  
384  #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
385  #define A_CNF_10B_T 0x0001
386  #define A_CNF_AUI 0x0002
387  #define A_CNF_10B_2 0x0004
388  #define A_CNF_MEDIA_TYPE 0x0070
389  #define A_CNF_MEDIA_AUTO 0x0070
390  #define A_CNF_MEDIA_10B_T 0x0020
391  #define A_CNF_MEDIA_AUI 0x0040
392  #define A_CNF_MEDIA_10B_2 0x0010
393  #define A_CNF_DC_DC_POLARITY 0x0080
394  #define A_CNF_NO_AUTO_POLARITY 0x2000
395  #define A_CNF_LOW_RX_SQUELCH 0x4000
396  #define A_CNF_EXTND_10B_2 0x8000
397  
398  #define PACKET_PAGE_OFFSET 0x8
399  
400  /*  Bit definitions for the ISA configuration word from the EEPROM */
401  #define INT_NO_MASK 0x000F
402  #define DMA_NO_MASK 0x0070
403  #define ISA_DMA_SIZE 0x0200
404  #define ISA_AUTO_RxDMA 0x0400
405  #define ISA_RxDMA 0x0800
406  #define DMA_BURST 0x1000
407  #define STREAM_TRANSFER 0x2000
408  #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
409  
410  /*  DMA controller registers */
411  #define DMA_BASE 0x00     /*  DMA controller base */
412  #define DMA_BASE_2 0x0C0    /*  DMA controller base */
413  
414  #define DMA_STAT 0x0D0    /*  DMA controller status register */
415  #define DMA_MASK 0x0D4    /*  DMA controller mask register */
416  #define DMA_MODE 0x0D6    /*  DMA controller mode register */
417  #define DMA_RESETFF 0x0D8    /*  DMA controller first/last flip flop */
418  
419  /*  DMA data */
420  #define DMA_DISABLE 0x04     /*  Disable channel n */
421  #define DMA_ENABLE 0x00     /*  Enable channel n */
422  /*  Demand transfers, incr. address, auto init, writes, ch. n */
423  #define DMA_RX_MODE 0x14
424  /*  Demand transfers, incr. address, auto init, reads, ch. n */
425  #define DMA_TX_MODE 0x18
426  
427  #define DMA_SIZE (16*1024) /*  Size of dma buffer - 16k */
428  
429  #define CS8900 0x0000
430  #define CS8920 0x4000
431  #define CS8920M 0x6000
432  #define REVISON_BITS 0x1F00
433  #define EEVER_NUMBER 0x12
434  #define CHKSUM_LEN 0x14
435  #define CHKSUM_VAL 0x0000
436  #define START_EEPROM_DATA 0x001c /*  Offset into eeprom for start of data */
437  #define IRQ_MAP_EEPROM_DATA 0x0046 /*  Offset into eeprom for the IRQ map */
438  #define IRQ_MAP_LEN 0x0004 /*  No of bytes to read for the IRQ map */
439  #define PNP_IRQ_FRMT 0x0022 /*  PNP small item IRQ format */
440  #define CS8900_IRQ_MAP 0x1c20 /*  This IRQ map is fixed */
441  
442  #define CS8920_NO_INTS 0x0F   /*  Max CS8920 interrupt select # */
443  
444  #define PNP_ADD_PORT 0x0279
445  #define PNP_WRITE_PORT 0x0A79
446  
447  #define GET_PNP_ISA_STRUCT 0x40
448  #define PNP_ISA_STRUCT_LEN 0x06
449  #define PNP_CSN_CNT_OFF 0x01
450  #define PNP_RD_PORT_OFF 0x02
451  #define PNP_FUNCTION_OK 0x00
452  #define PNP_WAKE 0x03
453  #define PNP_RSRC_DATA 0x04
454  #define PNP_RSRC_READY 0x01
455  #define PNP_STATUS 0x05
456  #define PNP_ACTIVATE 0x30
457  #define PNP_CNF_IO_H 0x60
458  #define PNP_CNF_IO_L 0x61
459  #define PNP_CNF_INT 0x70
460  #define PNP_CNF_DMA 0x74
461  #define PNP_CNF_MEM 0x48
462