| /openbmc/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/ |
| H A D | pearl_pcie_regs.h | 8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
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| H A D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) argument
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) argument
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| /openbmc/u-boot/board/micronas/vct/vctv/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| /openbmc/u-boot/board/micronas/vct/vcth2/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| /openbmc/u-boot/board/micronas/vct/vcth/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
32 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
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| H A D | reg_fwsram.h | 21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
37 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
39 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
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| H A D | reg_scc.h | 56 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
58 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
60 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
62 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
64 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
66 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
68 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
70 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
72 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
74 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_regs.h | 11 #define RING_EXCC(base) _MMIO((base) + 0x28) argument
12 #define RING_TAIL(base) _MMIO((base) + 0x30) argument
14 #define RING_HEAD(base) _MMIO((base) + 0x34) argument
18 #define RING_START(base) _MMIO((base) + 0x38) argument
19 #define RING_CTL(base) _MMIO((base) + 0x3c) argument
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40) argument
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44) argument
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48) argument
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) argument
55 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) argument
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| /openbmc/linux/drivers/gpu/drm/sun4i/ |
| H A D | sun8i_vi_scaler.h | 30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) argument
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28) argument
35 #define SUN50I_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
[all …]
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| H A D | sun8i_ui_layer.h | 17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
27 #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ argument
29 #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ argument
31 #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \ argument
33 #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \ argument
35 #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \ argument
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| H A D | sun8i_ui_scaler.h | 26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) argument
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) argument
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) argument
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) argument
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c) argument
31 #define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90) argument
32 #define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98) argument
33 #define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index)) argument
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| H A D | sun8i_vi_layer.h | 11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
21 #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ argument
23 #define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ argument
25 #define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ argument
27 #define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ argument
29 #define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ argument
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| /openbmc/linux/drivers/media/platform/samsung/s5p-jpeg/ |
| H A D | jpeg-hw-exynos4.c | 16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode()
52 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, in __exynos4_jpeg_set_img_fmt()
136 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, in __exynos4_jpeg_set_enc_out_fmt()
169 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) in exynos4_jpeg_set_interrupt()
183 unsigned int exynos4_jpeg_get_int_status(void __iomem *base) in exynos4_jpeg_get_int_status()
188 unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) in exynos4_jpeg_get_fifo_status()
193 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) in exynos4_jpeg_set_huf_table_enable()
207 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) in exynos4_jpeg_set_sys_int_enable()
219 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, in exynos4_jpeg_set_stream_buf_address()
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| /openbmc/linux/drivers/scsi/ |
| H A D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4()
45 static inline unsigned long nsp32_read4(unsigned int base, in nsp32_read4()
53 static inline void nsp32_mmio_write1(unsigned long base, in nsp32_mmio_write1()
64 static inline unsigned char nsp32_mmio_read1(unsigned long base, in nsp32_mmio_read1()
74 static inline void nsp32_mmio_write2(unsigned long base, in nsp32_mmio_write2()
85 static inline unsigned short nsp32_mmio_read2(unsigned long base, in nsp32_mmio_read2()
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| H A D | aha1740.h | 19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
25 #define BIOSADR(base) (base + 0x41) argument
26 #define INTDEF(base) (base + 0x42) argument
27 #define SCSIDEF(base) (base + 0x43) argument
28 #define BUSDEF(base) (base + 0x44) argument
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | 61 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio() argument
65 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio() argument
69 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio() argument
83 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio() argument
772 #define RING_REG(base) _MMIO((base) + 0xd0) in iterate_bdw_plus_mmio() argument
776 #define RING_REG(base) _MMIO((base) + 0x230) in iterate_bdw_plus_mmio() argument
780 #define RING_REG(base) _MMIO((base) + 0x234) in iterate_bdw_plus_mmio() argument
784 #define RING_REG(base) _MMIO((base) + 0x244) in iterate_bdw_plus_mmio() argument
788 #define RING_REG(base) _MMIO((base) + 0x370) in iterate_bdw_plus_mmio() argument
792 #define RING_REG(base) _MMIO((base) + 0x3a0) in iterate_bdw_plus_mmio() argument
[all …]
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3.c | 24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy()
101 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) in ddr3_init_ddremif()
112 int ddr3_ecc_support_rmw(u32 base) in ddr3_ecc_support_rmw()
124 static void ddr3_ecc_config(u32 base, u32 value) in ddr3_ecc_config()
148 static void ddr3_reset_data(u32 base, u32 ddr3_size) in ddr3_reset_data()
238 static void ddr3_ecc_init_range(u32 base) in ddr3_ecc_init_range()
251 void ddr3_enable_ecc(u32 base, int test) in ddr3_enable_ecc()
271 void ddr3_disable_ecc(u32 base) in ddr3_disable_ecc()
277 static void cic_init(u32 base) in cic_init()
290 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) in cic_map_cic_to_gic()
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| /openbmc/linux/arch/loongarch/lib/ |
| H A D | xor_simd.c | 19 #define LD(reg, base, offset) \ argument
21 #define ST(reg, base, offset) \ argument
25 #define LD_INOUT_LINE(base) \ argument
31 #define LD_AND_XOR_LINE(base) \ argument
41 #define ST_LINE(base) \ argument
62 #define LD(reg, base, offset) \ argument
64 #define ST(reg, base, offset) \ argument
68 #define LD_INOUT_LINE(base) \ argument
72 #define LD_AND_XOR_LINE(base) \ argument
78 #define ST_LINE(base) \ argument
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | fpu.S | 26 #define __REST_1FPVSR(n,c,base) \ argument
35 #define __REST_32FPVSRS(n,c,base) \ argument
44 #define __SAVE_32FPVSRS(n,c,base) \ argument
53 #define __REST_1FPVSR(n,b,base) REST_FPR(n, base) argument
54 #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) argument
55 #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) argument
57 #define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) argument
58 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) argument
59 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) argument
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| /openbmc/linux/include/linux/ |
| H A D | kstrtox.h | 30 static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigned long *res) in kstrtoul()
58 static inline int __must_check kstrtol(const char *s, unsigned int base, long *res) in kstrtol()
74 static inline int __must_check kstrtou64(const char *s, unsigned int base, u64 *res) in kstrtou64()
79 static inline int __must_check kstrtos64(const char *s, unsigned int base, s64 *res) in kstrtos64()
84 static inline int __must_check kstrtou32(const char *s, unsigned int base, u32 *res) in kstrtou32()
89 static inline int __must_check kstrtos32(const char *s, unsigned int base, s32 *res) in kstrtos32()
112 …t __must_check kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res) in kstrtou64_from_user()
117 …t __must_check kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res) in kstrtos64_from_user()
122 …t __must_check kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res) in kstrtou32_from_user()
127 …t __must_check kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res) in kstrtos32_from_user()
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| /openbmc/linux/lib/ |
| H A D | kstrtox.c | 26 const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix()
52 unsigned int _parse_integer_limit(const char *s, unsigned int base, unsigned long long *p, in _parse_integer_limit()
91 unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p) in _parse_integer()
96 static int _kstrtoull(const char *s, unsigned int base, unsigned long long *res) in _kstrtoull()
132 int kstrtoull(const char *s, unsigned int base, unsigned long long *res) in kstrtoull()
156 int kstrtoll(const char *s, unsigned int base, long long *res) in kstrtoll()
181 int _kstrtoul(const char *s, unsigned int base, unsigned long *res) in _kstrtoul()
197 int _kstrtol(const char *s, unsigned int base, long *res) in _kstrtol()
228 int kstrtouint(const char *s, unsigned int base, unsigned int *res) in kstrtouint()
259 int kstrtoint(const char *s, unsigned int base, int *res) in kstrtoint()
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-l2x0.c | 65 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec()
80 static inline void l2c_set_debug(void __iomem *base, unsigned long val) in l2c_set_debug()
91 static inline void l2c_unlock(void __iomem *base, unsigned num) in l2c_unlock()
103 static void l2c_configure(void __iomem *base) in l2c_configure()
112 static void l2c_enable(void __iomem *base, unsigned num_lock) in l2c_enable()
134 void __iomem *base = l2x0_base; in l2c_disable() local
143 static void l2c_save(void __iomem *base) in l2c_save()
150 void __iomem *base = l2x0_base; in l2c_resume() local
173 static void __l2c210_cache_sync(void __iomem *base) in __l2c210_cache_sync()
189 void __iomem *base = l2x0_base; in l2c210_inv_range() local
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| /openbmc/linux/drivers/media/platform/mediatek/jpeg/ |
| H A D | mtk_jpeg_dec_hw.c | 217 u32 mtk_jpeg_dec_get_int_status(void __iomem *base) in mtk_jpeg_dec_get_int_status()
246 void mtk_jpeg_dec_start(void __iomem *base) in mtk_jpeg_dec_start()
252 static void mtk_jpeg_dec_soft_reset(void __iomem *base) in mtk_jpeg_dec_soft_reset()
259 static void mtk_jpeg_dec_hard_reset(void __iomem *base) in mtk_jpeg_dec_hard_reset()
265 void mtk_jpeg_dec_reset(void __iomem *base) in mtk_jpeg_dec_reset()
272 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, in mtk_jpeg_dec_set_brz_factor()
282 static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank0()
293 static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank1()
301 static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_mem_stride()
308 static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_img_stride()
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| /openbmc/linux/drivers/scsi/pcmcia/ |
| H A D | nsp_io.h | 30 static inline void nsp_write(unsigned int base, in nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, in nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read()
113 static inline void nsp_fifo32_read(unsigned int base, in nsp_fifo32_read()
132 static inline void nsp_fifo8_write(unsigned int base, in nsp_fifo8_write()
150 static inline void nsp_fifo16_write(unsigned int base, in nsp_fifo16_write()
168 static inline void nsp_fifo32_write(unsigned int base, in nsp_fifo32_write()
178 static inline void nsp_mmio_write(unsigned long base, in nsp_mmio_write()
187 static inline unsigned char nsp_mmio_read(unsigned long base, in nsp_mmio_read()
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| /openbmc/linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | ext_caps.c | 24 static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base) in hci_extcap_hardware_id()
45 static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base) in hci_extcap_master_config()
59 static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base) in hci_extcap_multi_bus()
68 static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_modes()
88 static int hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_rates()
116 static int hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base) in hci_extcap_auto_command()
130 static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base) in hci_extcap_debug()
137 static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base) in hci_extcap_scheduled_cmd()
144 static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base) in hci_extcap_non_curr_master()
151 static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base) in hci_extcap_ccc_resp_conf()
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