Lines Matching +full:half +full:- +full:bus

1 /* SPDX-License-Identifier: GPL-2.0+ */
6  * Dante Su <dantesu@faraday-tech.com>
15 	} hccr;			/* 0x00 - 0x0f: hccr */
18 	} hcor;			/* 0x10 - 0x33: hcor */
21 	uint32_t bmcsr;	/* 0x40: Bus Monitor Control Status Register */
22 	uint32_t bmisr;	/* 0x44: Bus Monitor Interrupt Status Register */
23 	uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
33 /* Bus Monitor Control Status Register */
43 #define BMCSR_IRQLH     (1 << 3) /* IRQ triggered at level-high */
44 #define BMCSR_IRQLL     (0 << 3) /* IRQ triggered at level-low */
45 #define BMCSR_HALFSPD   (1 << 2) /* Half speed mode for FPGA test */
51 /* Bus Monitor Interrupt Status Register */
52 /* Bus Monitor Interrupt Enable Register */
56 #define BMISR_OVD       (1 << 1) /* over-current detected */