include/linux/serial_reg.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
45 #define UART_FCR	2	/* Out: FIFO Control Register */
89 #define UART_LCR	3	/* Out: Line Control Register */
95 #define UART_LCR_SBC		0x40 /* Set break control */
112 #define UART_MCR	4	/* Out: Modem Control Register */
116 #define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
158 #define UART_EFR_CTS		0x80 /* CTS flow control */
159 #define UART_EFR_RTS		0x40 /* RTS flow control */
161 #define UART_EFR_ECB		0x10 /* Enhanced control bit */
163  * the low four bits control software flow control
177 #define UART_TI752_TCR	6	/* I/O: transmission control register */
199 #define UART_FCTR	1	/* Feature Control Register */
200 #define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
222  * The Intel XScale on-chip UARTs define these bits
237  * Intel MID on-chip HSU (High Speed UART) defined bits
261 #define UART_ICR	0x05	/* Index Control Register */
264 #define UART_ACR	0x00	/* Additional Control Register */
270 #define UART_FCL	0x06	/* Flow Control Level Lower */
271 #define UART_FCH	0x07	/* Flow Control Level Higher */
277 #define UART_NMR	0x0D	/* Nine-bit Mode Register */
281  * The 16C950 Additional Control Register
285 #define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
293  * These definitions are for the RSA-DV II/S card, from
295  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
298 #define UART_RSA_BASE (-8)
304 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
330 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
347 #define UART_OMAP_SCR		0x10	/* Supplementary control register */
354 #define UART_OMAP_WER		0x17	/* Wake-up enable register */
361 #define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
375 #define UART_EXAR_FCTR		0x08	/* Feature Control Register */
377 #define UART_FCTR_EXAR_485	0x10	/* Auto 485 half duplex dir ctl */
383 #define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
384 #define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */