u-boot/include/fsl_fman.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * Copyright 2010-2011 Freescale Semiconductor, Inc.
19 	u32	fmbm_ier;	/* interrupt enable register */
24 	u32	fmbm_gde;	/* global debug enable */
36 	u32	fmqm_eien;	/* error interrupt enable register */
39 	u32	fmqm_ien;	/* interrupt enable register */
119 /* FMBM_RCFG - Rx configuration */
124 /* FMBM_RST - Rx status */
127 /* FMBM_RFCA - Rx frame command attributes */
132 /* FMBM_RSTC - Rx statistics */
133 #define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
136 	u32 fmbm_tcfg;	/* Tx configuration */
137 	u32 fmbm_tst;	/* Tx status */
138 	u32 fmbm_tda;	/* Tx DMA attributes */
139 	u32 fmbm_tfp;	/* Tx FIFO parameters */
140 	u32 fmbm_tfed;	/* Tx frame end data */
141 	u32 fmbm_ticp;	/* Tx internal context parameters */
142 	u32 fmbm_tfne;	/* Tx frame next engine */
143 	u32 fmbm_tfca;	/* Tx frame command attributes */
144 	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
145 	u32 fmbm_tfeqid;/* Tx error frame queue ID */
146 	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
147 	u32 fmbm_trlmts;/* Tx rate limiter scale */
148 	u32 fmbm_trlmt;	/* Tx rate limiter */
150 	u32 fmbm_tstc;	/* Tx statistics counters */
151 	u32 fmbm_tfrc;	/* Tx frame counter */
152 	u32 fmbm_tfdc;	/* Tx frames discard counter */
153 	u32 fmbm_tfledc;/* Tx frame length error discard counter */
154 	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
155 	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
157 	u32 fmbm_tpc;	/* Tx performance counters */
158 	u32 fmbm_tpcp;	/* Tx performance count parameters */
159 	u32 fmbm_tccn;	/* Tx cycle counter */
160 	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
161 	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
162 	u32 fmbm_tduc;	/* Tx DMA utilization counter */
163 	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
165 	u32 fmbm_tdcfg;	/* Tx debug configuration */
168 /* FMBM_TCFG - Tx configuration */
170 #define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
172 /* FMBM_TST - Tx status */
173 #define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
175 /* FMBM_TFCA - Tx frame command attributes */
180 /* FMBM_TSTC - Tx statistics counters */
183 /* FMBM_INIT - BMI initialization register */
186 /* FMBM_CFG1 - BMI configuration 1 */
191 /* FMBM_IEVR - interrupt event */
197 /* FMBM_IER - interrupt enable */
198 #define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
199 #define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
200 #define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
204 /* FMBM_PP - BMI Port Parameters */
206 #define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
208 #define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
210 /* FMBM_PFS - BMI Port FIFO Size */
214 /* FMQM_GC - global configuration */
215 #define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
216 #define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
217 #define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
223 /* FMQM_EIE - error interrupt event register */
224 #define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
228 /* FMQM_EIEN - error interrupt enable register */
229 #define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
233 /* FMQM_IE - interrupt event register */
234 #define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
237 /* FMQM_IEN - interrupt enable register */
238 #define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
241 /* NIA - next invoked action */
247 #define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
278 	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
282 /* FMDMSR - Fman DMA status register */
300 /* FMDMMR - FMan DMA mode register */
311 	u32	fmrie;		/* rams interrupt enable */
312 	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
314 	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
322 	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
331 	u32	fmfpee;		/* event and enable */
332 	u32	fpmcev[0x4];	/* CPU event 0-3 */
340 /* FMFP_PRC - FPM Port_ID Control Register */
351 /* FMFP_EE - FPM event and enable register */
356 #define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
357 #define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
358 #define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
359 #define FMFPEE_EHM		0x00000008 /* external halt enable */
368 /* FMFP_RCR - FMan Rams Control and Event */
379 #define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
398 	u8	res1[0x1000 - 0x138];