u-boot/include/fsl_dtsec.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
30 	u32	ipgifg;		/* inter-packet/inter-frame gap */
31 	u32	hafdup;		/* half-duplex control */
46 	u32	tr64;		/* Tx and Rx 64 bytes frame */
47 	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
48 	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
49 	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
50 	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
51 	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
52 	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
121 /* IEVENT - interrupt events register */
136 #define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
141 /* IMASK - interrupt mask register */
142 #define IMASK_BREN	0x80000000 /* Babbling receive enable */
143 #define IMASK_RXCEN	0x40000000 /* receive control enable */
144 #define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
145 #define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
146 #define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
147 #define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
148 #define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
149 #define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
151 #define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
152 #define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
153 #define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
154 #define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
155 #define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
156 #define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
157 #define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
161 /* ECNTRL - ethernet control register */
165 #define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
166 #define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
167 #define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
168 #define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
169 #define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
170 				      0- RGMII 10 Mbps, SGMII 10 Mbps */
171 #define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
172 #define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
176 /* TCTRL - Transmit control register */
177 #define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
178 #define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
182 /* RCTRL - Receive control register */
185 #define RCTRL_CFA	0x00008000 /* control frame accept enable */
187 #define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
191 #define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
192 #define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
195 /* MACCFG1 - MAC configuration 1 register */
205 #define MACCFG1_RX_EN		0x00000004 /* Rx enable */
207 #define MACCFG1_TX_EN		0x00000001 /* Tx enable */
210 /* MACCFG2 - MAC configuration 2 register */
216 #define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
217 #define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
218 #define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
220 #define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */