u-boot/include/ddr_spd.h

14 	unsigned char info_size;   /*  0 # bytes written into serial memory */
15 	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
16 	unsigned char mem_type;    /*  2 Fundamental memory type */
17 	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
18 	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
19 	unsigned char nrows;       /*  5 Number of DIMM Banks */
20 	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
21 	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
22 	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
23 	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
24 	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
25 	unsigned char config;      /* 11 DIMM Configuration type */
26 	unsigned char refresh;     /* 12 Refresh Rate/Type */
27 	unsigned char primw;       /* 13 Primary SDRAM Width */
28 	unsigned char ecw;         /* 14 Error Checking SDRAM width */
29 	unsigned char min_delay;   /* 15 for Back to Back Random Address */
30 	unsigned char burstl;      /* 16 Burst Lengths Supported */
31 	unsigned char nbanks;      /* 17 # of Banks on SDRAM Device */
32 	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
33 	unsigned char cs_lat;      /* 19 CS# Latency */
34 	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
35 	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
36 	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
37 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
38 	unsigned char clk_access2; /* 24 SDRAM Access from
40 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
42 	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
43 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
44 	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
45 	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
46 	unsigned char bank_dens;   /* 31 Density of each bank on module */
47 	unsigned char ca_setup;    /* 32 Addr + Cmd Setup Time Before Clk */
48 	unsigned char ca_hold;     /* 33 Addr + Cmd Hold Time After Clk */
49 	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
50 	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
51 	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
52 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
53 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
54 	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
55 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
56 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
57 	unsigned char res_46;      /* 46 Reserved */
58 	unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
59 	unsigned char res_48_61[14]; /* 48-61 Reserved */
60 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
61 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
62 	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
63 	unsigned char mloc;        /* 72 Manufacturing Location */
64 	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
65 	unsigned char rev[2];      /* 91 Revision Code */
66 	unsigned char mdate[2];    /* 93 Manufacturing Date */
67 	unsigned char sernum[4];   /* 95 Assembly Serial Number */
68 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
77 	unsigned char info_size;   /*  0 # bytes written into serial memory */
78 	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
79 	unsigned char mem_type;    /*  2 Fundamental memory type */
80 	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
81 	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
82 	unsigned char mod_ranks;   /*  5 Number of DIMM Ranks */
83 	unsigned char dataw;       /*  6 Module Data Width */
84 	unsigned char res_7;       /*  7 Reserved */
85 	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
86 	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
87 	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
88 	unsigned char config;      /* 11 DIMM Configuration type */
89 	unsigned char refresh;     /* 12 Refresh Rate/Type */
90 	unsigned char primw;       /* 13 Primary SDRAM Width */
91 	unsigned char ecw;         /* 14 Error Checking SDRAM width */
92 	unsigned char res_15;      /* 15 Reserved */
93 	unsigned char burstl;      /* 16 Burst Lengths Supported */
94 	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
95 	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
96 	unsigned char mech_char;   /* 19 DIMM Mechanical Characteristics */
97 	unsigned char dimm_type;   /* 20 DIMM type information */
98 	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
99 	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
100 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
101 	unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
102 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
103 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
104 	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
105 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
106 	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
107 	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
108 	unsigned char rank_dens;   /* 31 Density of each rank on module */
109 	unsigned char ca_setup;    /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
110 	unsigned char ca_hold;     /* 33 Addr+Cmd Hold Time After Clk (tIH) */
111 	unsigned char data_setup;  /* 34 Data Input Setup Time
113 	unsigned char data_hold;   /* 35 Data Input Hold Time
115 	unsigned char twr;         /* 36 Write Recovery time tWR */
116 	unsigned char twtr;        /* 37 Int write to read delay tWTR */
117 	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
118 	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
119 	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
120 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
121 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
122 	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
123 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
124 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
125 	unsigned char pll_relock;  /* 46 PLL Relock time */
126 	unsigned char t_casemax;    /* 47 Tcasemax */
127 	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
129 	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
132 	unsigned char dt2n_dt2q;   /* 50 DRAM Case Temperature Rise from Ambient
135 	unsigned char dt2p;        /* 51 DRAM Case Temperature Rise from Ambient
137 	unsigned char dt3n;        /* 52 DRAM Case Temperature Rise from Ambient
139 	unsigned char dt3pfast;    /* 53 DRAM Case Temperature Rise from Ambient
142 	unsigned char dt3pslow;    /* 54 DRAM Case Temperature Rise from Ambient
145 	unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
148 	unsigned char dt5b;        /* 56 DRAM Case Temperature Rise from Ambient
150 	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
153 	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
155 	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
158 	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
160 	unsigned char dtregact;    /* 61 Register Case Temperature Rise from
163 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
164 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
165 	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
166 	unsigned char mloc;        /* 72 Manufacturing Location */
167 	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
168 	unsigned char rev[2];      /* 91 Revision Code */
169 	unsigned char mdate[2];    /* 93 Manufacturing Date */
170 	unsigned char sernum[4];   /* 95 Assembly Serial Number */
171 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
177 	unsigned char info_size_crc;   /*  0 # bytes written into serial memory,
179 	unsigned char spd_rev;         /*  1 Total # bytes of SPD mem device */
180 	unsigned char mem_type;        /*  2 Key Byte / Fundamental mem type */
181 	unsigned char module_type;     /*  3 Key Byte / Module Type */
182 	unsigned char density_banks;   /*  4 SDRAM Density and Banks */
183 	unsigned char addressing;      /*  5 SDRAM Addressing */
184 	unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
185 	unsigned char organization;    /*  7 Module Organization */
186 	unsigned char bus_width;       /*  8 Module Memory Bus Width */
187 	unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
189 	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
190 	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
191 	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
192 	unsigned char res_13;          /* 13 Reserved */
193 	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
195 	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
197 	unsigned char taa_min;         /* 16 Min CAS Latency Time */
198 	unsigned char twr_min;         /* 17 Min Write REcovery Time */
199 	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
200 	unsigned char trrd_min;        /* 19 Min Row Active to
202 	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
203 	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
204 	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
206 	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
208 	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
209 	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
210 	unsigned char twtr_min;        /* 26 Min Internal Write to
212 	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
214 	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
215 	unsigned char tfaw_min;        /* 29 Min Four Activate Window
217 	unsigned char opt_features;    /* 30 SDRAM Optional Features */
218 	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
219 	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
220 	unsigned char device_type;     /* 33 SDRAM device type */
226 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
232 			unsigned char mod_height;
234 			unsigned char mod_thickness;
236 			unsigned char ref_raw_card;
239 			unsigned char addr_mapping;
241 			unsigned char res_64_116[53];
245 			unsigned char mod_height;
247 			unsigned char mod_thickness;
249 			unsigned char ref_raw_card;
251 			unsigned char modu_attr;
253 			unsigned char thermal;
255 			unsigned char reg_id_lo;
257 			unsigned char reg_id_hi;
259 			unsigned char reg_rev;
261 			unsigned char reg_type;
263 			unsigned char rcw[8];
265 		unsigned char uc[57]; /* 60-116 Module-Specific Section */
269 	unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
270 	unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
271 	unsigned char mloc;            /* 119 Mfg Location */
272 	unsigned char mdate[2];        /* 120-121 Mfg Date */
273 	unsigned char sernum[4];       /* 122-125 Module Serial Number */
276 	unsigned char crc[2];          /* 126-127 SPD CRC */
279 	unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
280 	unsigned char mrev[2];         /* 146-147 Module Revision Code */
282 	unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
283 	unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
285 	unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
286 	unsigned char cust[80];        /* 176-255 Open for Customer Use */