Lines Matching +full:ras +full:- +full:to +full:- +full:cas
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
10 * Format from "JEDEC Standard No. 21-C,
29 unsigned char min_delay; /* 15 for Back to Back Random Address */
32 unsigned char cas_lat; /* 18 CAS# Latencies Supported */
37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
39 Clk @ CL=X-0.5 (tAC) */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
51 unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
52 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
53 unsigned char trfc; /* 42 Min Auto to Active period tRFC */
55 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
59 unsigned char res_48_61[14]; /* 48-61 Reserved */
61 unsigned char cksum; /* 63 Checksum for bytes 0-62 */
62 unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */
68 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
95 unsigned char cas_lat; /* 18 CAS# Latencies Supported */
100 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */
101 unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
102 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */
103 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
105 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
106 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
107 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
116 unsigned char twtr; /* 37 Int write to read delay tWTR */
117 unsigned char trtp; /* 38 Int read to precharge delay tRTP */
119 unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
120 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
121 unsigned char trfc; /* 42 Min Auto to Active period tRFC */
123 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
128 Top (Case) to Ambient (Psi T-A DRAM) */
130 due to Activate-Precharge/Mode Bits
133 due to Precharge/Quiet Standby
136 due to Precharge Power-Down (DT2P) */
138 due to Active Standby (DT3N) */
140 due to Active Power-Down with
143 due to Active Power-Down with Slow
146 due to Page Open Burst Read/DT4R4W
149 due to Burst Refresh (DT5B) */
151 due to Bank Interleave Reads with
152 Auto-Precharge (DT7) */
154 Top (Case) to Ambient (Psi T-A PLL) */
156 from Top (Case) to Ambient
157 (Psi T-A Register) */
159 due to PLL Active (DT PLL Active) */
161 Ambient due to Register Active/Mode Bit
164 unsigned char cksum; /* 63 Checksum for bytes 0-62 */
165 unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */
171 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */
176 /* General Section: Bytes 0-59 */
193 unsigned char caslat_lsb; /* 14 CAS Latencies Supported,
195 unsigned char caslat_msb; /* 15 CAS Latencies Supported,
197 unsigned char taa_min; /* 16 Min CAS Latency Time */
199 unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */
200 unsigned char trrd_min; /* 19 Min Row Active to
204 unsigned char tras_min_lsb; /* 22 Min Active to Precharge
206 unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh
210 unsigned char twtr_min; /* 26 Min Internal Write to
212 unsigned char trtp_min; /* 27 Min Internal Read to Precharge
226 unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
228 /* Module-Specific Section: Bytes 60-116 */
238 Edge Connector to DRAM */
240 /* 64-116 (Unbuffered) Reserved */
262 /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
265 unsigned char uc[57]; /* 60-116 Module-Specific Section */
268 /* Unique Module ID: Bytes 117-125 */
269 unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
270 unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
272 unsigned char mdate[2]; /* 120-121 Mfg Date */
273 unsigned char sernum[4]; /* 122-125 Module Serial Number */
275 /* CRC: Bytes 126-127 */
276 unsigned char crc[2]; /* 126-127 SPD CRC */
278 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
279 unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */
280 unsigned char mrev[2]; /* 146-147 Module Revision Code */
282 unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
283 unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
285 unsigned char msd[26]; /* 150-175 Mfg's Specific Data */
286 unsigned char cust[80]; /* 176-255 Open for Customer Use */
290 /* From JEEC Standard No. 21-C release 23A */
292 /* General Section: Bytes 0-127 */
313 uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
314 uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
315 uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
316 uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
317 uint8_t taa_min; /* 24 Min CAS Latency Time */
318 uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
334 uint8_t res_41[60-41]; /* 41 Rserved */
335 uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
336 uint8_t res_78[117-78]; /* 78~116, Reserved */
346 /* CRC: Bytes 126-127 */
347 uint8_t crc[2]; /* 126-127 SPD CRC */
349 /* Module-Specific Section: Bytes 128-255 */
359 Edge Connector to DRAM */
362 uint8_t res_132[254-132];
383 /* 136 Address mapping from register to DRAM */
388 u8 res_137[254 - 139];
409 /* 136 Address mapping from register to DRAM */
474 uint8_t res_155[254-155]; /* Reserved */
478 uint8_t uc[128]; /* 128-255 Module-Specific Section */
481 uint8_t res_256[320-256]; /* 256~319 Reserved */
497 uint8_t user[512-384]; /* 384~511 End User Programmable */
523 /* DIMM Type for DDR2 SPD (according to v1.3) */