Lines Matching +full:half +full:- +full:bus
1 /* SPDX-License-Identifier: GPL-2.0+ */
62 * L2CR setup -- make sure this is right for your board!
77 * Base addresses -- Note these are effective addresses where the
178 /* EPLD - User switches, board id, LEDs */
182 /* Local bus SDRAM 128MB */
184 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
186 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
190 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
194 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
198 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
222 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
258 * Addresses are mapped 1-1.
288 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
332 * BAT0 2G Cacheable, non-guarded
341 * BAT1 1G Cache-inhibited, guarded
342 * 0x8000_0000 512M PCI-Express 1 Memory
343 * 0xa000_0000 512M PCI-Express 2 Memory
353 * BAT2 512M Cache-inhibited, guarded
363 * BAT3 4M Cache-inhibited, guarded
384 * BAT4 32M Cache-inhibited, guarded
385 * 0xe200_0000 16M PCI-Express 1 I/O
386 * 0xe300_0000 16M PCI-Express 2 I/0
396 * BAT5 128K Cacheable, non-guarded
405 * BAT6 32M Cache-inhibited, guarded
491 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
492 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
502 "bootm $loadaddr - $dtbaddr"