drivers/watchdog/armada-37xx-wdt.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Marvell Armada 37xx SoC Watchdog Driver
21 	u64 timeout;  member
25  * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
45 	writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));  in set_counter_value()
46 	writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));  in set_counter_value()
51 	setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);  in counter_enable()
56 	clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);  in counter_disable()
63 	reg = readl(priv->reg + CNTR_CTRL(id));  in init_counter()
65 		return -EBUSY;  in init_counter()
79 	writel(reg, priv->reg + CNTR_CTRL(id));  in init_counter()
88 	if (!priv->timeout)  in a37xx_wdt_reset()
89 		return -EINVAL;  in a37xx_wdt_reset()
102 	/* first we set timeout to 0 */  in a37xx_wdt_expire_now()
114 static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)  in a37xx_wdt_start()  argument
128 	priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;  in a37xx_wdt_start()
131 	set_counter_value(priv, 1, priv->timeout);  in a37xx_wdt_start()
146 	writel(0, priv->sel_reg);  in a37xx_wdt_stop()
159 	priv->sel_reg = (void __iomem *)addr;  in a37xx_wdt_probe()
164 	priv->reg = (void __iomem *)addr;  in a37xx_wdt_probe()
166 	priv->clk_rate = (ulong)get_ref_clk() * 1000000;  in a37xx_wdt_probe()
169 	 * We use counter 1 as watchdog timer, therefore we only set bit  in a37xx_wdt_probe()
170 	 * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on  in a37xx_wdt_probe()
173 	writel(1 << 1, priv->sel_reg);  in a37xx_wdt_probe()
178 	return -ENODEV;  in a37xx_wdt_probe()
189 	{ .compatible = "marvell,armada-3700-wdt" },