Lines Matching +full:i2c +full:- +full:lt +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0+
20 #include <dt-bindings/clock/rk3288-cru.h>
46 writel(SEL_24M, ®s->analog_ctl_2); in rk_edp_init_refclk()
47 writel(REF_CLK_24M, ®s->pll_reg_1); in rk_edp_init_refclk()
50 V2L_CUR_SEL_1MA, ®s->pll_reg_2); in rk_edp_init_refclk()
54 ®s->pll_reg_3); in rk_edp_init_refclk()
58 ®s->pll_reg_5); in rk_edp_init_refclk()
60 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg); in rk_edp_init_refclk()
64 ®s->tx_common); in rk_edp_init_refclk()
67 ®s->dp_aux); in rk_edp_init_refclk()
70 ®s->dp_bias); in rk_edp_init_refclk()
73 ®s->dp_reserv2); in rk_edp_init_refclk()
79 writel(INT_POL, ®s->int_ctl); in rk_edp_init_interrupt()
82 writel(0xff, ®s->common_int_sta_1); in rk_edp_init_interrupt()
83 writel(0x4f, ®s->common_int_sta_2); in rk_edp_init_interrupt()
84 writel(0xff, ®s->common_int_sta_3); in rk_edp_init_interrupt()
85 writel(0x27, ®s->common_int_sta_4); in rk_edp_init_interrupt()
86 writel(0x7f, ®s->dp_int_sta); in rk_edp_init_interrupt()
89 writel(0x00, ®s->common_int_mask_1); in rk_edp_init_interrupt()
90 writel(0x00, ®s->common_int_mask_2); in rk_edp_init_interrupt()
91 writel(0x00, ®s->common_int_mask_3); in rk_edp_init_interrupt()
92 writel(0x00, ®s->common_int_mask_4); in rk_edp_init_interrupt()
93 writel(0x00, ®s->int_sta_mask); in rk_edp_init_interrupt()
98 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N); in rk_edp_enable_sw_function()
105 val = readl(®s->dp_debug_ctl); in rk_edp_get_pll_locked()
114 writel(0x00, ®s->dp_pd); in rk_edp_init_analog_func()
115 writel(PLL_LOCK_CHG, ®s->common_int_sta_1); in rk_edp_init_analog_func()
117 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); in rk_edp_init_analog_func()
123 return -ETIMEDOUT; in rk_edp_init_analog_func()
127 /* Enable Serdes FIFO function and Link symbol clock domain module */ in rk_edp_init_analog_func()
128 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N | in rk_edp_init_analog_func()
138 writel(AUX_FUNC_EN_N, ®s->dp_int_sta); in rk_edp_init_aux()
141 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N); in rk_edp_init_aux()
144 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl); in rk_edp_init_aux()
146 /* Enable AUX channel module */ in rk_edp_init_aux()
147 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N); in rk_edp_init_aux()
154 setbits_le32(®s->aux_ch_ctl_2, AUX_EN); in rk_edp_aux_enable()
157 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN)) in rk_edp_aux_enable()
161 return -ETIMEDOUT; in rk_edp_aux_enable()
169 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) { in rk_edp_is_aux_reply()
171 return -ETIMEDOUT; in rk_edp_is_aux_reply()
174 writel(RPLY_RECEIV, ®s->dp_int_sta); in rk_edp_is_aux_reply()
183 /* Enable AUX CH operation */ in rk_edp_start_aux_transaction()
186 debug("AUX CH enable timeout!\n"); in rk_edp_start_aux_transaction()
197 val = readl(®s->dp_int_sta); in rk_edp_start_aux_transaction()
199 writel(AUX_ERR, ®s->dp_int_sta); in rk_edp_start_aux_transaction()
200 return -EIO; in rk_edp_start_aux_transaction()
204 val = readl(®s->dp_int_sta); in rk_edp_start_aux_transaction()
207 return -EIO; in rk_edp_start_aux_transaction()
229 writel(BUF_CLR, ®s->buf_data_ctl); in rk_edp_dpcd_transfer()
232 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0); in rk_edp_dpcd_transfer()
233 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8); in rk_edp_dpcd_transfer()
234 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16); in rk_edp_dpcd_transfer()
239 * If Bit 3 is 0, I2C transaction. in rk_edp_dpcd_transfer()
246 writel(*data++, ®s->buf_data[i]); in rk_edp_dpcd_transfer()
252 writel(val, ®s->aux_ch_ctl_1); in rk_edp_dpcd_transfer()
267 *data++ = (u8)readl(®s->buf_data[i]); in rk_edp_dpcd_transfer()
270 length -= len; in rk_edp_dpcd_transfer()
297 if (edp->link_train.revision < 0x11) in rk_edp_link_power_up()
300 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); in rk_edp_link_power_up()
307 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); in rk_edp_link_power_up()
313 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink in rk_edp_link_power_up()
325 values[0] = edp->link_train.link_rate; in rk_edp_link_configure()
326 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
328 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values, in rk_edp_link_configure()
337 for (i = 0; i < edp->link_train.lane_count; i++) in rk_edp_set_link_training()
338 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]); in rk_edp_set_link_training()
343 return link_status[r - DPCD_LANE0_1_STATUS]; in edp_link_status()
349 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status, in rk_edp_dpcd_read_link_status()
370 return -EIO; in rk_edp_clock_recovery()
385 return -EIO; in rk_edp_channel_eq()
389 return -EIO; in rk_edp_channel_eq()
461 struct rk3288_edp *regs = edp->regs; in rk_edp_link_train_cr()
469 writel(value, ®s->dp_training_ptn_set); in rk_edp_link_train_cr()
473 memset(edp->train_set, '\0', sizeof(edp->train_set)); in rk_edp_link_train_cr()
481 rk_edp_set_link_training(edp, edp->train_set); in rk_edp_link_train_cr()
483 edp->train_set, in rk_edp_link_train_cr()
484 edp->link_train.lane_count); in rk_edp_link_train_cr()
497 edp->link_train.lane_count); in rk_edp_link_train_cr()
501 for (i = 0; i < edp->link_train.lane_count; i++) { in rk_edp_link_train_cr()
502 if ((edp->train_set[i] & in rk_edp_link_train_cr()
506 if (i == edp->link_train.lane_count) { in rk_edp_link_train_cr()
511 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in rk_edp_link_train_cr()
521 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in rk_edp_link_train_cr()
524 edp_get_adjust_train(status, edp->link_train.lane_count, in rk_edp_link_train_cr()
525 edp->train_set); in rk_edp_link_train_cr()
531 debug("clock recovery at voltage %d pre-emphasis %d\n", in rk_edp_link_train_cr()
532 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in rk_edp_link_train_cr()
533 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in rk_edp_link_train_cr()
541 struct rk3288_edp *regs = edp->regs; in rk_edp_link_train_ce()
549 writel(value, ®s->dp_training_ptn_set); in rk_edp_link_train_ce()
557 rk_edp_set_link_training(edp, edp->train_set); in rk_edp_link_train_ce()
562 return -1; in rk_edp_link_train_ce()
566 edp->link_train.lane_count); in rk_edp_link_train_ce()
569 edp_get_adjust_train(status, edp->link_train.lane_count, in rk_edp_link_train_ce()
570 edp->train_set); in rk_edp_link_train_ce()
578 debug("channel eq at voltage %d pre-emphasis %d\n", in rk_edp_link_train_ce()
579 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in rk_edp_link_train_ce()
580 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in rk_edp_link_train_ce()
591 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values, in rk_edp_init_training()
596 edp->link_train.revision = values[0]; in rk_edp_init_training()
597 edp->link_train.link_rate = values[1]; in rk_edp_init_training()
598 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK; in rk_edp_init_training()
601 edp->link_train.link_rate * 27 / 100, in rk_edp_init_training()
602 edp->link_train.link_rate * 27 % 100, in rk_edp_init_training()
603 edp->link_train.lane_count); in rk_edp_init_training()
605 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) && in rk_edp_init_training()
606 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) { in rk_edp_init_training()
608 edp->link_train.link_rate); in rk_edp_init_training()
609 return -EPERM; in rk_edp_init_training()
612 if (edp->link_train.lane_count == 0) { in rk_edp_init_training()
614 edp->link_train.lane_count); in rk_edp_init_training()
615 return -EPERM; in rk_edp_init_training()
632 writel(edp->link_train.link_rate, &edp->regs->link_bw_set); in rk_edp_hw_link_training()
633 writel(edp->link_train.lane_count, &edp->regs->lane_count_set); in rk_edp_hw_link_training()
642 writel(HW_LT_EN, &edp->regs->dp_hw_link_training); in rk_edp_hw_link_training()
645 val = readl(&edp->regs->dp_hw_link_training); in rk_edp_hw_link_training()
653 return -EIO; in rk_edp_hw_link_training()
666 writel(device_addr, ®s->aux_addr_7_0); in rk_edp_select_i2c_device()
667 writel(0x0, ®s->aux_addr_15_8); in rk_edp_select_i2c_device()
668 writel(0x0, ®s->aux_addr_19_16); in rk_edp_select_i2c_device()
671 writel(val_addr, ®s->buf_data[0]); in rk_edp_select_i2c_device()
674 * Set I2C transaction and write address in rk_edp_select_i2c_device()
676 * If Bit 3 is 0, I2C transaction. in rk_edp_select_i2c_device()
679 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1); in rk_edp_select_i2c_device()
703 writel(BUF_CLR, ®s->buf_data_ctl); in rk_edp_i2c_read()
706 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY); in rk_edp_i2c_read()
721 * Set I2C transaction and write data in rk_edp_i2c_read()
723 * If Bit 3 is 0, I2C transaction. in rk_edp_i2c_read()
726 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1); in rk_edp_i2c_read()
738 val = readl(®s->aux_rx_comm); in rk_edp_i2c_read()
750 val = readl(®s->buf_data[cur_data_idx]); in rk_edp_i2c_read()
764 printf("DP LT init failed!\n"); in rk_edp_set_link_train()
778 ®s->common_int_sta_1); in rk_edp_init_video()
779 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2); in rk_edp_init_video()
780 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8); in rk_edp_init_video()
785 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); in rk_edp_config_video_slave_mode()
794 setbits_le32(®s->sys_ctl_4, FIX_M_VID); in rk_edp_set_video_cr_mn()
795 writel(m_value & 0xff, ®s->m_vid_0); in rk_edp_set_video_cr_mn()
796 writel((m_value >> 8) & 0xff, ®s->m_vid_1); in rk_edp_set_video_cr_mn()
797 writel((m_value >> 16) & 0xff, ®s->m_vid_2); in rk_edp_set_video_cr_mn()
799 writel(n_value & 0xf, ®s->n_vid_0); in rk_edp_set_video_cr_mn()
800 writel((n_value >> 8) & 0xff, ®s->n_vid_1); in rk_edp_set_video_cr_mn()
801 writel((n_value >> 16) & 0xff, ®s->n_vid_2); in rk_edp_set_video_cr_mn()
803 clrbits_le32(®s->sys_ctl_4, FIX_M_VID); in rk_edp_set_video_cr_mn()
805 writel(0x00, ®s->n_vid_0); in rk_edp_set_video_cr_mn()
806 writel(0x80, ®s->n_vid_1); in rk_edp_set_video_cr_mn()
807 writel(0x00, ®s->n_vid_2); in rk_edp_set_video_cr_mn()
818 val = readl(®s->sys_ctl_1); in rk_edp_is_video_stream_clock_on()
821 writel(val, ®s->sys_ctl_1); in rk_edp_is_video_stream_clock_on()
822 val = readl(®s->sys_ctl_1); in rk_edp_is_video_stream_clock_on()
826 val = readl(®s->sys_ctl_2); in rk_edp_is_video_stream_clock_on()
829 writel(val, ®s->sys_ctl_2); in rk_edp_is_video_stream_clock_on()
830 val = readl(®s->sys_ctl_2); in rk_edp_is_video_stream_clock_on()
836 return -ETIMEDOUT; in rk_edp_is_video_stream_clock_on()
846 val = readl(&edp->regs->sys_ctl_3); in rk_edp_is_video_stream_on()
849 writel(val, &edp->regs->sys_ctl_3); in rk_edp_is_video_stream_on()
851 val = readl(&edp->regs->sys_ctl_3); in rk_edp_is_video_stream_on()
856 return -ETIMEDOUT; in rk_edp_is_video_stream_on()
863 rk_edp_config_video_slave_mode(edp->regs); in rk_edp_config_video()
865 if (!rk_edp_get_pll_locked(edp->regs)) { in rk_edp_config_video()
867 return -ETIMEDOUT; in rk_edp_config_video()
870 ret = rk_edp_is_video_stream_clock_on(edp->regs); in rk_edp_config_video()
875 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0); in rk_edp_config_video()
878 clrbits_le32(&edp->regs->video_ctl_10, F_SEL); in rk_edp_config_video()
881 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); in rk_edp_config_video()
883 /* Enable video at next frame */ in rk_edp_config_video()
884 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN); in rk_edp_config_video()
891 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL); in rockchip_edp_force_hpd()
898 val = readl(&edp->regs->sys_ctl_3); in rockchip_edp_get_plug_in_status()
940 rk_edp_init_video(priv->regs); in rk_edp_enable()
946 ret = panel_enable_backlight(priv->panel); in rk_edp_enable()
963 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER, in rk_edp_read_edid()
976 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, in rk_edp_read_edid()
998 priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev); in rk_edp_ofdata_to_platdata()
999 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk_edp_ofdata_to_platdata()
1007 struct rk3288_edp *regs = priv->regs; in rk_edp_remove()
1009 setbits_le32(®s->video_ctl_1, VIDEO_MUTE); in rk_edp_remove()
1010 clrbits_le32(®s->video_ctl_1, VIDEO_EN); in rk_edp_remove()
1011 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); in rk_edp_remove()
1012 setbits_le32(®s->func_en_1, SW_FUNC_EN_N); in rk_edp_remove()
1021 struct rk3288_edp *regs = priv->regs; in rk_edp_probe()
1026 &priv->panel); in rk_edp_probe()
1029 dev->name, ret); in rk_edp_probe()
1033 int vop_id = uc_plat->source_id; in rk_edp_probe()
1046 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); in rk_edp_probe()
1053 __func__, uc_plat->src_dev->name, ret); in rk_edp_probe()
1058 rk_setreg(&priv->grf->soc_con12, 1 << 4); in rk_edp_probe()
1061 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5)); in rk_edp_probe()
1078 .enable = rk_edp_enable,
1082 { .compatible = "rockchip,rk3288-edp" },