Lines Matching full:csr
319 u16 fifo_count = 0, csr; in txstate() local
338 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
344 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
346 musb_ep->end_point.name, csr); in txstate()
350 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
352 musb_ep->end_point.name, csr); in txstate()
358 csr); in txstate()
365 /* setup DMA, then program endpoint CSR */ in txstate()
392 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
394 musb_writew(epio, MUSB_TXCSR, csr in txstate()
396 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
397 csr |= (MUSB_TXCSR_DMAENAB | in txstate()
401 csr |= (MUSB_TXCSR_DMAENAB in txstate()
405 csr |= MUSB_TXCSR_AUTOSET; in txstate()
407 csr &= ~MUSB_TXCSR_P_UNDERRUN; in txstate()
409 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
414 /* program endpoint CSR first, then setup DMA */ in txstate()
415 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); in txstate()
416 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | in txstate()
420 | csr); in txstate()
423 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
443 csr &= ~MUSB_TXCSR_DMAENAB; in txstate()
444 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
467 csr |= MUSB_TXCSR_TXPKTRDY; in txstate()
468 csr &= ~MUSB_TXCSR_P_UNDERRUN; in txstate()
469 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
487 u16 csr; in musb_g_tx() local
499 csr = musb_readw(epio, MUSB_TXCSR); in musb_g_tx()
500 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); in musb_g_tx()
508 if (csr & MUSB_TXCSR_P_SENTSTALL) { in musb_g_tx()
509 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
510 csr &= ~MUSB_TXCSR_P_SENTSTALL; in musb_g_tx()
511 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
515 if (csr & MUSB_TXCSR_P_UNDERRUN) { in musb_g_tx()
517 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
518 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); in musb_g_tx()
519 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
536 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { in musb_g_tx()
538 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
539 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | in musb_g_tx()
541 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
543 csr = musb_readw(epio, MUSB_TXCSR); in musb_g_tx()
546 epnum, csr, musb_ep->dma->actual_len, request); in musb_g_tx()
566 if (csr & MUSB_TXCSR_TXPKTRDY) in musb_g_tx()
642 u16 csr = musb_readw(epio, MUSB_RXCSR); in rxstate() local
666 if (csr & MUSB_RXCSR_P_SENDSTALL) { in rxstate()
668 musb_ep->end_point.name, csr); in rxstate()
691 csr &= ~(MUSB_RXCSR_AUTOCLEAR in rxstate()
693 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; in rxstate()
694 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
699 if (csr & MUSB_RXCSR_RXPKTRDY) { in rxstate()
746 csr |= MUSB_RXCSR_AUTOCLEAR; in rxstate()
747 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
748 csr |= MUSB_RXCSR_DMAENAB; in rxstate()
749 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
757 csr | MUSB_RXCSR_DMAMODE); in rxstate()
758 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
763 csr |= MUSB_RXCSR_AUTOCLEAR; in rxstate()
764 csr |= MUSB_RXCSR_DMAENAB; in rxstate()
765 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
815 csr &= ~MUSB_RXCSR_DMAMODE; in rxstate()
816 csr |= (MUSB_RXCSR_DMAENAB | in rxstate()
819 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
826 csr |= MUSB_RXCSR_DMAMODE; in rxstate()
827 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
877 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); in rxstate()
878 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
890 csr |= MUSB_RXCSR_P_WZC_BITS; in rxstate()
891 csr &= ~MUSB_RXCSR_RXPKTRDY; in rxstate()
892 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
906 u16 csr; in musb_g_rx() local
928 csr = musb_readw(epio, MUSB_RXCSR); in musb_g_rx()
932 csr, dma ? " (dma)" : "", request); in musb_g_rx()
934 if (csr & MUSB_RXCSR_P_SENTSTALL) { in musb_g_rx()
935 csr |= MUSB_RXCSR_P_WZC_BITS; in musb_g_rx()
936 csr &= ~MUSB_RXCSR_P_SENTSTALL; in musb_g_rx()
937 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
941 if (csr & MUSB_RXCSR_P_OVERRUN) { in musb_g_rx()
942 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ in musb_g_rx()
943 csr &= ~MUSB_RXCSR_P_OVERRUN; in musb_g_rx()
944 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
950 if (csr & MUSB_RXCSR_INCOMPRX) { in musb_g_rx()
957 dev_dbg(musb->controller, "%s busy, csr %04x\n", in musb_g_rx()
958 musb_ep->end_point.name, csr); in musb_g_rx()
962 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { in musb_g_rx()
963 csr &= ~(MUSB_RXCSR_AUTOCLEAR in musb_g_rx()
967 MUSB_RXCSR_P_WZC_BITS | csr); in musb_g_rx()
972 epnum, csr, in musb_g_rx()
983 csr &= ~MUSB_RXCSR_RXPKTRDY; in musb_g_rx()
984 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
994 csr = musb_readw(epio, MUSB_RXCSR); in musb_g_rx()
995 if ((csr & MUSB_RXCSR_RXPKTRDY) && in musb_g_rx()
1036 u16 csr; in musb_gadget_enable() local
1116 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; in musb_gadget_enable()
1119 csr |= MUSB_TXCSR_FLUSHFIFO; in musb_gadget_enable()
1121 csr |= MUSB_TXCSR_P_ISO; in musb_gadget_enable()
1124 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1126 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1158 csr = musb_readw(regs, MUSB_TXCSR); in musb_gadget_enable()
1159 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); in musb_gadget_enable()
1160 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1163 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; in musb_gadget_enable()
1165 csr |= MUSB_RXCSR_P_ISO; in musb_gadget_enable()
1167 csr |= MUSB_RXCSR_DISNYET; in musb_gadget_enable()
1170 musb_writew(regs, MUSB_RXCSR, csr); in musb_gadget_enable()
1171 musb_writew(regs, MUSB_RXCSR, csr); in musb_gadget_enable()
1435 u16 csr; in musb_gadget_set_halt() local
1462 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_set_halt()
1463 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_gadget_set_halt()
1475 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_set_halt()
1476 csr |= MUSB_TXCSR_P_WZC_BITS in musb_gadget_set_halt()
1479 csr |= MUSB_TXCSR_P_SENDSTALL; in musb_gadget_set_halt()
1481 csr &= ~(MUSB_TXCSR_P_SENDSTALL in musb_gadget_set_halt()
1483 csr &= ~MUSB_TXCSR_TXPKTRDY; in musb_gadget_set_halt()
1484 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_set_halt()
1486 csr = musb_readw(epio, MUSB_RXCSR); in musb_gadget_set_halt()
1487 csr |= MUSB_RXCSR_P_WZC_BITS in musb_gadget_set_halt()
1491 csr |= MUSB_RXCSR_P_SENDSTALL; in musb_gadget_set_halt()
1493 csr &= ~(MUSB_RXCSR_P_SENDSTALL in musb_gadget_set_halt()
1495 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_set_halt()
1557 u16 csr, int_txe; in musb_gadget_fifo_flush() local
1569 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_fifo_flush()
1570 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_gadget_fifo_flush()
1571 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; in musb_gadget_fifo_flush()
1577 csr &= ~MUSB_TXCSR_TXPKTRDY; in musb_gadget_fifo_flush()
1578 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_fifo_flush()
1580 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_fifo_flush()
1583 csr = musb_readw(epio, MUSB_RXCSR); in musb_gadget_fifo_flush()
1584 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; in musb_gadget_fifo_flush()
1585 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_fifo_flush()
1586 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_fifo_flush()