Lines Matching +full:0 +full:xc400
36 #define DWC3_EVENT_TYPE_MASK 0xfe
38 #define DWC3_EVENT_TYPE_DEV 0
42 #define DWC3_DEVICE_EVENT_DISCONNECT 0
54 #define DWC3_GEVNTCOUNT_MASK 0xfffc
55 #define DWC3_GSNPSID_MASK 0xffff0000
56 #define DWC3_GSNPSREV_MASK 0xffff
59 #define DWC3_XHCI_REGS_START 0x0
60 #define DWC3_XHCI_REGS_END 0x7fff
61 #define DWC3_GLOBALS_REGS_START 0xc100
62 #define DWC3_GLOBALS_REGS_END 0xc6ff
63 #define DWC3_DEVICE_REGS_START 0xc700
64 #define DWC3_DEVICE_REGS_END 0xcbff
65 #define DWC3_OTG_REGS_START 0xcc00
66 #define DWC3_OTG_REGS_END 0xccff
69 #define DWC3_GSBUSCFG0 0xc100
70 #define DWC3_GSBUSCFG1 0xc104
71 #define DWC3_GTXTHRCFG 0xc108
72 #define DWC3_GRXTHRCFG 0xc10c
73 #define DWC3_GCTL 0xc110
74 #define DWC3_GEVTEN 0xc114
75 #define DWC3_GSTS 0xc118
76 #define DWC3_GSNPSID 0xc120
77 #define DWC3_GGPIO 0xc124
78 #define DWC3_GUID 0xc128
79 #define DWC3_GUCTL 0xc12c
80 #define DWC3_GBUSERRADDR0 0xc130
81 #define DWC3_GBUSERRADDR1 0xc134
82 #define DWC3_GPRTBIMAP0 0xc138
83 #define DWC3_GPRTBIMAP1 0xc13c
84 #define DWC3_GHWPARAMS0 0xc140
85 #define DWC3_GHWPARAMS1 0xc144
86 #define DWC3_GHWPARAMS2 0xc148
87 #define DWC3_GHWPARAMS3 0xc14c
88 #define DWC3_GHWPARAMS4 0xc150
89 #define DWC3_GHWPARAMS5 0xc154
90 #define DWC3_GHWPARAMS6 0xc158
91 #define DWC3_GHWPARAMS7 0xc15c
92 #define DWC3_GDBGFIFOSPACE 0xc160
93 #define DWC3_GDBGLTSSM 0xc164
94 #define DWC3_GPRTBIMAP_HS0 0xc180
95 #define DWC3_GPRTBIMAP_HS1 0xc184
96 #define DWC3_GPRTBIMAP_FS0 0xc188
97 #define DWC3_GPRTBIMAP_FS1 0xc18c
99 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
100 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
102 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
104 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
106 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
107 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
109 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
110 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
111 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
112 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
114 #define DWC3_GHWPARAMS8 0xc600
117 #define DWC3_DCFG 0xc700
118 #define DWC3_DCTL 0xc704
119 #define DWC3_DEVTEN 0xc708
120 #define DWC3_DSTS 0xc70c
121 #define DWC3_DGCMDPAR 0xc710
122 #define DWC3_DGCMD 0xc714
123 #define DWC3_DALEPENA 0xc720
124 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
125 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
126 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
127 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
130 #define DWC3_OCFG 0xcc00
131 #define DWC3_OCTL 0xcc04
132 #define DWC3_OEVT 0xcc08
133 #define DWC3_OEVTEN 0xcc0C
134 #define DWC3_OSTS 0xcc10
142 #define DWC3_GCTL_CLK_BUS (0)
160 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
181 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
182 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
186 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
190 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
198 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
201 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
206 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
210 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
218 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
220 #define DWC3_DCFG_SPEED_MASK (7 << 0)
221 #define DWC3_DCFG_SUPERSPEED (4 << 0)
222 #define DWC3_DCFG_HIGHSPEED (0 << 0)
223 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
224 #define DWC3_DCFG_LOWSPEED (2 << 0)
225 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
234 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
240 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
249 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
261 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
263 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
266 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
286 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
301 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
306 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
309 #define DWC3_DSTS_CONNECTSPD (7 << 0)
311 #define DWC3_DSTS_SUPERSPEED (4 << 0)
312 #define DWC3_DSTS_HIGHSPEED (0 << 0)
313 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
314 #define DWC3_DSTS_LOWSPEED (2 << 0)
315 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
318 #define DWC3_DGCMD_SET_LMP 0x01
319 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
320 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
323 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
324 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
326 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
327 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
328 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
329 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
336 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
337 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
338 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
340 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
341 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
346 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
352 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
353 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
354 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
355 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
356 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
357 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
359 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
361 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
362 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
363 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
365 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
368 #define DWC3_DEPCMD_TYPE_CONTROL 0
394 #define DWC3_EVENT_PENDING (1UL << 0)
401 #define DWC3_EP_FLAG_STALLED (1 << 0)
446 #define DWC3_EP_ENABLED (1 << 0)
470 DWC3_PHY_UNKNOWN = 0,
476 DWC3_EP0_UNKNOWN = 0,
483 EP0_UNCONNECTED = 0,
491 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
492 DWC3_LINK_STATE_U1 = 0x01,
493 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
494 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
495 DWC3_LINK_STATE_SS_DIS = 0x04,
496 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
497 DWC3_LINK_STATE_SS_INACT = 0x06,
498 DWC3_LINK_STATE_POLL = 0x07,
499 DWC3_LINK_STATE_RECOV = 0x08,
500 DWC3_LINK_STATE_HRESET = 0x09,
501 DWC3_LINK_STATE_CMPLY = 0x0a,
502 DWC3_LINK_STATE_LPBK = 0x0b,
503 DWC3_LINK_STATE_RESET = 0x0e,
504 DWC3_LINK_STATE_RESUME = 0x0f,
505 DWC3_LINK_STATE_MASK = 0x0f,
509 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
511 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
512 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
514 #define DWC3_TRBSTS_OK 0
520 #define DWC3_TRB_CTRL_HWO (1 << 0)
524 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
527 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
577 #define DWC3_MODE(n) ((n) & 0x7)
579 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
582 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
585 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
586 #define DWC3_NUM_EPS_MASK (0x3f << 12)
593 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
671 * 0 - utmi_sleep_n
693 * 0 - -6dB de-emphasis
745 #define DWC3_REVISION_173A 0x5533173a
746 #define DWC3_REVISION_175A 0x5533175a
747 #define DWC3_REVISION_180A 0x5533180a
748 #define DWC3_REVISION_183A 0x5533183a
749 #define DWC3_REVISION_185A 0x5533185a
750 #define DWC3_REVISION_187A 0x5533187a
751 #define DWC3_REVISION_188A 0x5533188a
752 #define DWC3_REVISION_190A 0x5533190a
753 #define DWC3_REVISION_194A 0x5533194a
754 #define DWC3_REVISION_200A 0x5533200a
755 #define DWC3_REVISION_202A 0x5533202a
756 #define DWC3_REVISION_210A 0x5533210a
757 #define DWC3_REVISION_220A 0x5533220a
758 #define DWC3_REVISION_230A 0x5533230a
759 #define DWC3_REVISION_240A 0x5533240a
760 #define DWC3_REVISION_250A 0x5533250a
761 #define DWC3_REVISION_260A 0x5533260a
762 #define DWC3_REVISION_270A 0x5533270a
763 #define DWC3_REVISION_280A 0x5533280a
833 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
834 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
835 #define DWC3_DEPEVT_XFERNOTREADY 0x03
836 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
837 #define DWC3_DEPEVT_STREAMEVT 0x06
838 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
869 * 0x00 - Reserved
870 * 0x01 - XferComplete
871 * 0x02 - XferInProgress
872 * 0x03 - XferNotReady
873 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
874 * 0x05 - Reserved
875 * 0x06 - StreamEvt
876 * 0x07 - EPCmdCmplt
894 #define DEPEVT_STATUS_BUSERR (1 << 0)
913 * @device_event: indicates it's a device event. Should read as 0x00
915 * 0 - DisconnEvt
944 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
988 #define DWC3_HAS_PERIPHERAL BIT(0)
1002 { return 0; } in dwc3_host_init()
1018 { return 0; } in dwc3_gadget_init()
1022 { return 0; } in dwc3_gadget_set_test_mode()
1024 { return 0; } in dwc3_gadget_get_link_state()
1027 { return 0; } in dwc3_gadget_set_link_state()
1031 { return 0; } in dwc3_send_gadget_ep_cmd()
1034 { return 0; } in dwc3_send_gadget_generic_command()