1 // SPDX-License-Identifier: GPL-2.0+
18 #include <asm/u-boot-x86.h>
40 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)  in native_calibrate_tsc()
54 		switch (gd->arch.x86_model) {  in native_calibrate_tsc()
77 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)  in cpu_mhz_from_cpuid()
87  * According to Intel 64 and IA-32 System Programming Guide,
107 	/* TNG - Intel Atom processor Z3400 series */
109 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
111 	/* ANN - Intel Atom processor Z3500 series */
113 	/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
130 	return -1;  in match_cpu()
133 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
149 	u32 lo, hi, ratio, freq_id, freq;  in cpu_mhz_from_msr()  local
153 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)  in cpu_mhz_from_msr()
156 	cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);  in cpu_mhz_from_msr()
161 		rdmsr(MSR_PLATFORM_INFO, lo, hi);  in cpu_mhz_from_msr()
162 		ratio = (lo >> 8) & 0xff;  in cpu_mhz_from_msr()
164 		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);  in cpu_mhz_from_msr()
167 	debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);  in cpu_mhz_from_msr()
171 		freq = 100000;  in cpu_mhz_from_msr()
172 		debug("Using frequency: %u KHz\n", freq);  in cpu_mhz_from_msr()
174 		/* Get FSB FREQ ID */  in cpu_mhz_from_msr()
175 		rdmsr(MSR_FSB_FREQ, lo, hi);  in cpu_mhz_from_msr()
176 		freq_id = lo & 0x7;  in cpu_mhz_from_msr()
177 		freq = id_to_freq(cpu_index, freq_id);  in cpu_mhz_from_msr()
178 		debug("Resolved frequency ID: %u, frequency: %u KHz\n",  in cpu_mhz_from_msr()
179 		      freq_id, freq);  in cpu_mhz_from_msr()
182 	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */  in cpu_mhz_from_msr()
183 	res = freq * ratio / 1000;  in cpu_mhz_from_msr()
192  * non-virtualized hardware.
196  *  - the PIT is running at roughly 1.19MHz
198  *  - each IO is going to take about 1us on real hardware,
201  *    update - anything else implies a unacceptably slow CPU
204  *  - with 256 PIT ticks to read the value, we have 214us to
208  *  - We're doing 2 reads per loop (LSB, MSB), and we expect
213  *  - if the PIT is stuck, and we see *many* more reads, we
243 	*deltap = rdtsc() - prev_tsc;  in pit_expect_msb()
272 	 * Counter 2, mode 0 (one-shot), binary count  in quick_pit_calibrate()
276 	 * final output frequency as a decrement-by-one),  in quick_pit_calibrate()
289 	 * to do that is to just read back the 16-bit counter  in quick_pit_calibrate()
296 			if (!pit_expect_msb(0xff-i, &delta, &d2))  in quick_pit_calibrate()
302 			delta -= tsc;  in quick_pit_calibrate()
313 			if (!pit_verify_msb(0xfe - i))  in quick_pit_calibrate()
331 	 * kHz = ticks / time-in-seconds / 1000;  in quick_pit_calibrate()
332 	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000  in quick_pit_calibrate()
333 	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)  in quick_pit_calibrate()
354 	return get_ms_timer() - base;  in get_timer()
374 	while ((int64_t)(stop - get_ticks()) > 0)  in __udelay()
390 	*count = now_tick - gd->arch.tsc_base;  in tsc_timer_get_count()
397 	if (gd->arch.tsc_base)  in tsc_timer_ensure_setup()
399 	gd->arch.tsc_base = rdtsc();  in tsc_timer_ensure_setup()
401 	if (!gd->arch.clock_rate) {  in tsc_timer_ensure_setup()
426 		gd->arch.clock_rate = fast_calibrate * 1000000;  in tsc_timer_ensure_setup()
436 	if (!gd->arch.clock_rate) {  in tsc_timer_probe()
441 		if (!uc_priv->clock_rate)  in tsc_timer_probe()
444 		uc_priv->clock_rate = gd->arch.clock_rate;  in tsc_timer_probe()
459 	return gd->arch.clock_rate;  in timer_early_get_rate()
464 	return rdtsc() - gd->arch.tsc_base;  in timer_early_get_count()
472 	{ .compatible = "x86,tsc-timer", },