drivers/spi/xilinx_spi.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Xilinx SPI driver
5  * Supports 8 bit SPI transfers only, with or w/o FIFO
9  * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
12  * Copyright (c) 2005-2008 Analog Devices Inc.
20 #include <spi.h>
27  * Xilinx SPI Register Definitions
30  * [2]:	[0]/ip_documentation/axi_spi_ds742.pdf
34 /* SPI Control Register (spicr), [1] p9, [2] p8 */
42 #define SPICR_MASTER_MODE	BIT(2)
46 /* SPI Status Register (spisr), [1] p11, [2] p10 */
50 #define SPISR_TX_EMPTY		BIT(2)
54 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
59 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
64 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
69 /* SPI Software Reset Register (ssr) */
83 /* xilinx spi register set */
93 	u32 spicr;	/* SPI Control Register (SPICR) */
94 	u32 spisr;	/* SPI Status Register (SPISR) */
95 	u32 spidtr;	/* SPI Data Transmit Register (SPIDTR) */
96 	u32 spidrr;	/* SPI Data Receive Register (SPIDRR) */
97 	u32 spissr;	/* SPI Slave Select Register (SPISSR) */
98 	u32 spitfor;	/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
99 	u32 spirfor;	/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
102 /* xilinx spi priv */
114 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_probe()
116 	priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);  in xilinx_spi_probe()
118 	priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);  in xilinx_spi_probe()
120 	writel(SPISSR_RESET_VALUE, &regs->srr);  in xilinx_spi_probe()
129 	struct xilinx_spi_regs *regs = priv->regs;  in spi_cs_activate()
131 	writel(SPISSR_ACT(cs), &regs->spissr);  in spi_cs_activate()
138 	struct xilinx_spi_regs *regs = priv->regs;  in spi_cs_deactivate()
140 	writel(SPISSR_OFF, &regs->spissr);  in spi_cs_deactivate()
147 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_claim_bus()
149 	writel(SPISSR_OFF, &regs->spissr);  in xilinx_spi_claim_bus()
150 	writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);  in xilinx_spi_claim_bus()
159 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_release_bus()
161 	writel(SPISSR_OFF, &regs->spissr);  in xilinx_spi_release_bus()
162 	writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);  in xilinx_spi_release_bus()
171 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_fill_txfifo()
175 	while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&  in xilinx_spi_fill_txfifo()
176 	       i < priv->fifo_depth) {  in xilinx_spi_fill_txfifo()
180 		writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);  in xilinx_spi_fill_txfifo()
181 		txbytes--;  in xilinx_spi_fill_txfifo()
191 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_read_rxfifo()
195 	while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {  in xilinx_spi_read_rxfifo()
196 		d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;  in xilinx_spi_read_rxfifo()
200 		rxbytes--;  in xilinx_spi_read_rxfifo()
213 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_startup_block()
226 	for ( ; priv->startup < 2; priv->startup++) {  in xilinx_spi_startup_block()
228 		reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;  in xilinx_spi_startup_block()
229 		writel(reg, &regs->spicr);  in xilinx_spi_startup_block()
233 		if (priv->startup) {  in xilinx_spi_startup_block()
235 			spi_cs_activate(dev, slave_plat->cs);  in xilinx_spi_startup_block()
246 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_xfer()
248 	/* assume spi core configured to do 8 bit transfers */  in xilinx_spi_xfer()
258 	      bus->seq, slave_plat->cs, bitlen, bytes, flags);  in xilinx_spi_xfer()
271 		spi_cs_activate(dev, slave_plat->cs);  in xilinx_spi_xfer()
275 	 * the spi controller. SPI clock is passing through STARTUP  in xilinx_spi_xfer()
283 		reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;  in xilinx_spi_xfer()
284 		writel(reg, &regs->spicr);  in xilinx_spi_xfer()
285 		txbytes -= count;  in xilinx_spi_xfer()
289 		ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,  in xilinx_spi_xfer()
298 		rxbytes -= count;  in xilinx_spi_xfer()
315 	priv->freq = speed;  in xilinx_spi_set_speed()
317 	debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,  in xilinx_spi_set_speed()
318 	      priv->freq);  in xilinx_spi_set_speed()
326 	struct xilinx_spi_regs *regs = priv->regs;  in xilinx_spi_set_mode()
329 	spicr = readl(&regs->spicr);  in xilinx_spi_set_mode()
339 	writel(spicr, &regs->spicr);  in xilinx_spi_set_mode()
340 	priv->mode = mode;  in xilinx_spi_set_mode()
342 	debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,  in xilinx_spi_set_mode()
343 	      priv->mode);  in xilinx_spi_set_mode()
357 	{ .compatible = "xlnx,xps-spi-2.00.a" },
358 	{ .compatible = "xlnx,xps-spi-2.00.b" },