Lines Matching +full:dc +full:- +full:dc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/ti-common/ti-edma3.h>
36 #define QSPI_WLEN(n) ((n-1) << 19)
85 u32 dc; member
111 unsigned int mode; member
113 u32 dc; member
123 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_spi_set_speed()
132 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()
133 &priv->base->clk_ctrl); in ti_spi_set_speed()
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
140 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); in ti_qspi_cs_deactivate()
142 readl(&priv->base->cmd); in ti_qspi_cs_deactivate()
145 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) in __ti_qspi_set_mode() argument
147 priv->dc = 0; in __ti_qspi_set_mode()
148 if (mode & SPI_CPHA) in __ti_qspi_set_mode()
149 priv->dc |= QSPI_CKPHA(0); in __ti_qspi_set_mode()
150 if (mode & SPI_CPOL) in __ti_qspi_set_mode()
151 priv->dc |= QSPI_CKPOL(0); in __ti_qspi_set_mode()
152 if (mode & SPI_CS_HIGH) in __ti_qspi_set_mode()
153 priv->dc |= QSPI_CSPOL(0); in __ti_qspi_set_mode()
160 writel(priv->dc, &priv->base->dc); in __ti_qspi_claim_bus()
161 writel(0, &priv->base->cmd); in __ti_qspi_claim_bus()
162 writel(0, &priv->base->data); in __ti_qspi_claim_bus()
164 priv->dc <<= cs * 8; in __ti_qspi_claim_bus()
165 writel(priv->dc, &priv->base->dc); in __ti_qspi_claim_bus()
172 writel(0, &priv->base->dc); in __ti_qspi_release_bus()
173 writel(0, &priv->base->cmd); in __ti_qspi_release_bus()
174 writel(0, &priv->base->data); in __ti_qspi_release_bus()
193 uint words = bitlen >> 3; /* fixed 8-bit word length */ in __ti_qspi_xfer()
201 writel(MM_SWITCH, &priv->base->memswitch); in __ti_qspi_xfer()
202 if (priv->ctrl_mod_mmap) in __ti_qspi_xfer()
203 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); in __ti_qspi_xfer()
206 writel(~MM_SWITCH, &priv->base->memswitch); in __ti_qspi_xfer()
207 if (priv->ctrl_mod_mmap) in __ti_qspi_xfer()
208 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); in __ti_qspi_xfer()
213 return -1; in __ti_qspi_xfer()
217 return -1; in __ti_qspi_xfer()
221 priv->cmd = 0; in __ti_qspi_xfer()
222 priv->cmd |= QSPI_WLEN(8); in __ti_qspi_xfer()
223 priv->cmd |= QSPI_EN_CS(cs); in __ti_qspi_xfer()
224 if (priv->mode & SPI_3WIRE) in __ti_qspi_xfer()
225 priv->cmd |= QSPI_3_PIN; in __ti_qspi_xfer()
226 priv->cmd |= 0xfff; in __ti_qspi_xfer()
232 u32 cmd = priv->cmd; in __ti_qspi_xfer()
239 writel(data, &priv->base->data3); in __ti_qspi_xfer()
241 writel(data, &priv->base->data2); in __ti_qspi_xfer()
243 writel(data, &priv->base->data1); in __ti_qspi_xfer()
245 writel(data, &priv->base->data); in __ti_qspi_xfer()
250 writeb(*txp, &priv->base->data); in __ti_qspi_xfer()
253 debug("tx cmd %08x dc %08x\n", in __ti_qspi_xfer()
254 cmd | QSPI_WR_SNGL, priv->dc); in __ti_qspi_xfer()
255 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd); in __ti_qspi_xfer()
256 status = readl(&priv->base->status); in __ti_qspi_xfer()
259 if (--timeout < 0) { in __ti_qspi_xfer()
261 return -1; in __ti_qspi_xfer()
263 status = readl(&priv->base->status); in __ti_qspi_xfer()
269 debug("rx cmd %08x dc %08x\n", in __ti_qspi_xfer()
270 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); in __ti_qspi_xfer()
271 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd); in __ti_qspi_xfer()
272 status = readl(&priv->base->status); in __ti_qspi_xfer()
275 if (--timeout < 0) { in __ti_qspi_xfer()
277 return -1; in __ti_qspi_xfer()
279 status = readl(&priv->base->status); in __ti_qspi_xfer()
281 *rxp++ = readl(&priv->base->data); in __ti_qspi_xfer()
284 status, *(rxp-1)); in __ti_qspi_xfer()
286 words -= xfer_len; in __ti_qspi_xfer()
296 /* TODO: control from sf layer to here through dm-spi */
353 struct spi_slave *slave = &priv->slave; in ti_spi_setup_spi_register()
358 slave->mode |= SPI_RX_QUAD; in ti_spi_setup_spi_register()
366 writel(memval, &priv->base->setup0); in ti_spi_setup_spi_register()
370 unsigned int max_hz, unsigned int mode) in spi_setup_slave() argument
385 priv->base = (struct ti_qspi_regs *)QSPI_BASE; in spi_setup_slave()
386 priv->mode = mode; in spi_setup_slave()
388 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; in spi_setup_slave()
389 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; in spi_setup_slave()
390 priv->fclk = QSPI_DRA7XX_FCLK; in spi_setup_slave()
392 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; in spi_setup_slave()
393 priv->fclk = QSPI_FCLK; in spi_setup_slave()
402 return &priv->slave; in spi_setup_slave()
415 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); in spi_claim_bus()
416 __ti_qspi_set_mode(priv, priv->mode); in spi_claim_bus()
417 return __ti_qspi_claim_bus(priv, priv->slave.cs); in spi_claim_bus()
423 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); in spi_release_bus()
433 priv->slave.bus, priv->slave.cs, bitlen, flags); in spi_xfer()
434 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); in spi_xfer()
444 u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); in __ti_qspi_setup_memorymap() local
447 writel(0, &priv->base->setup0); in __ti_qspi_setup_memorymap()
453 switch (mode) { in __ti_qspi_setup_memorymap()
458 slave->mode |= SPI_RX_QUAD; in __ti_qspi_setup_memorymap()
472 writel(memval, &priv->base->setup0); in __ti_qspi_setup_memorymap()
485 static int ti_qspi_set_mode(struct udevice *bus, uint mode) in ti_qspi_set_mode() argument
488 return __ti_qspi_set_mode(priv, mode); in ti_qspi_set_mode()
498 bus = dev->parent; in ti_qspi_claim_bus()
501 if (slave_plat->cs > priv->num_cs) { in ti_qspi_claim_bus()
503 return -EINVAL; in ti_qspi_claim_bus()
508 return __ti_qspi_claim_bus(priv, slave_plat->cs); in ti_qspi_claim_bus()
517 bus = dev->parent; in ti_qspi_release_bus()
533 bus = dev->parent; in ti_qspi_xfer()
536 if (slave->cs > priv->num_cs) { in ti_qspi_xfer()
538 return -EINVAL; in ti_qspi_xfer()
541 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); in ti_qspi_xfer()
548 priv->fclk = dev_get_driver_data(bus); in ti_qspi_probe()
562 "syscon-chipselects", &syscon); in map_syscon_chipselects()
576 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus), in map_syscon_chipselects()
577 "syscon-chipselects", &len); in map_syscon_chipselects()
595 const void *blob = gd->fdt_blob; in ti_qspi_ofdata_to_platdata()
598 priv->ctrl_mod_mmap = map_syscon_chipselects(bus); in ti_qspi_ofdata_to_platdata()
599 priv->base = map_physmem(devfdt_get_addr(bus), in ti_qspi_ofdata_to_platdata()
601 priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0, in ti_qspi_ofdata_to_platdata()
604 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); in ti_qspi_ofdata_to_platdata()
605 if (priv->max_hz < 0) { in ti_qspi_ofdata_to_platdata()
607 return -ENODEV; in ti_qspi_ofdata_to_platdata()
609 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); in ti_qspi_ofdata_to_platdata()
611 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, in ti_qspi_ofdata_to_platdata()
612 (int)priv->base, priv->max_hz); in ti_qspi_ofdata_to_platdata()
623 slave->memory_map = priv->memory_map; in ti_qspi_child_pre_probe()
636 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
637 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},