Lines Matching +full:tegra20 +full:- +full:sflash
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2010-2013 NVIDIA Corporation
15 #include <asm/arch-tegra/clk_rst.h>
79 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ in tegra20_sflash_cs_info()
81 return -ENODEV; in tegra20_sflash_cs_info()
88 struct tegra_spi_platdata *plat = bus->platdata; in tegra20_sflash_ofdata_to_platdata()
89 const void *blob = gd->fdt_blob; in tegra20_sflash_ofdata_to_platdata()
92 plat->base = devfdt_get_addr(bus); in tegra20_sflash_ofdata_to_platdata()
93 plat->periph_id = clock_decode_periph_id(bus); in tegra20_sflash_ofdata_to_platdata()
95 if (plat->periph_id == PERIPH_ID_NONE) { in tegra20_sflash_ofdata_to_platdata()
97 plat->periph_id); in tegra20_sflash_ofdata_to_platdata()
98 return -FDT_ERR_NOTFOUND; in tegra20_sflash_ofdata_to_platdata()
102 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in tegra20_sflash_ofdata_to_platdata()
104 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in tegra20_sflash_ofdata_to_platdata()
105 "spi-deactivate-delay", 0); in tegra20_sflash_ofdata_to_platdata()
106 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", in tegra20_sflash_ofdata_to_platdata()
107 __func__, plat->base, plat->periph_id, plat->frequency, in tegra20_sflash_ofdata_to_platdata()
108 plat->deactivate_delay_us); in tegra20_sflash_ofdata_to_platdata()
118 priv->regs = (struct spi_regs *)plat->base; in tegra20_sflash_probe()
120 priv->last_transaction_us = timer_get_us(); in tegra20_sflash_probe()
121 priv->freq = plat->frequency; in tegra20_sflash_probe()
122 priv->periph_id = plat->periph_id; in tegra20_sflash_probe()
125 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, in tegra20_sflash_probe()
126 priv->freq); in tegra20_sflash_probe()
133 struct udevice *bus = dev->parent; in tegra20_sflash_claim_bus()
135 struct spi_regs *regs = priv->regs; in tegra20_sflash_claim_bus()
139 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, in tegra20_sflash_claim_bus()
140 priv->freq); in tegra20_sflash_claim_bus()
145 writel(reg, ®s->status); in tegra20_sflash_claim_bus()
146 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); in tegra20_sflash_claim_bus()
149 * Use sw-controlled CS, so we can clock in data after ReadID, etc. in tegra20_sflash_claim_bus()
151 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; in tegra20_sflash_claim_bus()
152 if (priv->mode & 2) in tegra20_sflash_claim_bus()
154 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | in tegra20_sflash_claim_bus()
156 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); in tegra20_sflash_claim_bus()
159 * SPI pins on Tegra20 are muxed - change pinmux later due to UART in tegra20_sflash_claim_bus()
171 struct udevice *bus = dev->parent; in spi_cs_activate()
176 if (pdata->deactivate_delay_us && in spi_cs_activate()
177 priv->last_transaction_us) { in spi_cs_activate()
179 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
180 if (delay_us < pdata->deactivate_delay_us) in spi_cs_activate()
181 udelay(pdata->deactivate_delay_us - delay_us); in spi_cs_activate()
185 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); in spi_cs_activate()
190 struct udevice *bus = dev->parent; in spi_cs_deactivate()
195 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); in spi_cs_deactivate()
198 if (pdata->deactivate_delay_us) in spi_cs_deactivate()
199 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
206 struct udevice *bus = dev->parent; in tegra20_sflash_xfer()
208 struct spi_regs *regs = priv->regs; in tegra20_sflash_xfer()
216 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); in tegra20_sflash_xfer()
218 return -1; in tegra20_sflash_xfer()
223 reg = readl(®s->status); in tegra20_sflash_xfer()
224 writel(reg, ®s->status); /* Clear all SPI events via R/W */ in tegra20_sflash_xfer()
227 reg = readl(®s->command); in tegra20_sflash_xfer()
229 writel(reg, ®s->command); in tegra20_sflash_xfer()
230 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); in tegra20_sflash_xfer()
235 /* handle data in 32-bit chunks */ in tegra20_sflash_xfer()
249 num_bytes -= bytes; in tegra20_sflash_xfer()
253 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, in tegra20_sflash_xfer()
254 bytes * 8 - 1); in tegra20_sflash_xfer()
255 writel(tmpdout, ®s->tx_fifo); in tegra20_sflash_xfer()
256 setbits_le32(®s->command, SPI_CMD_GO); in tegra20_sflash_xfer()
265 status = readl(®s->status); in tegra20_sflash_xfer()
276 tmpdin = readl(®s->rx_fifo); in tegra20_sflash_xfer()
281 for (i = bytes - 1; i >= 0; --i) { in tegra20_sflash_xfer()
294 writel(readl(®s->status), ®s->status); in tegra20_sflash_xfer()
301 tmpdin, readl(®s->status)); in tegra20_sflash_xfer()
305 return -1; in tegra20_sflash_xfer()
313 struct tegra_spi_platdata *plat = bus->platdata; in tegra20_sflash_set_speed()
316 if (speed > plat->frequency) in tegra20_sflash_set_speed()
317 speed = plat->frequency; in tegra20_sflash_set_speed()
318 priv->freq = speed; in tegra20_sflash_set_speed()
319 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); in tegra20_sflash_set_speed()
328 priv->mode = mode; in tegra20_sflash_set_mode()
329 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); in tegra20_sflash_set_mode()
343 { .compatible = "nvidia,tegra20-sflash" },