25 #define DEBUG_RK_SPI	0
74 	writel(enable ? 1 : 0, &regs->enr);  in rkspi_enable_chip()
92 	if (clk_div > 0xfffe) {  in rkspi_set_clk()
93 		clk_div = 0xfffe;  in rkspi_set_clk()
99 	clk_div = (clk_div + 1) & 0xfffe;  in rkspi_set_clk()
103 	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);  in rkspi_set_clk()
111 	start = get_timer(0);  in rkspi_wait_till_not_busy()
119 	return 0;  in rkspi_wait_till_not_busy()
151 	writel(0, &regs->ser);  in spi_cs_deactivate()
166 	plat->base = dtplat->reg[0];  in conv_of_platdata()
168 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);  in conv_of_platdata()
169 	if (ret < 0)  in conv_of_platdata()
171 	dev->req_seq = 0;  in conv_of_platdata()
173 	return 0;  in conv_of_platdata()
186 	ret = clk_get_by_index(bus, 0, &priv->clk);  in rockchip_spi_ofdata_to_platdata()
187 	if (ret < 0) {  in rockchip_spi_ofdata_to_platdata()
196 		dev_read_u32_default(bus, "spi-deactivate-delay", 0);  in rockchip_spi_ofdata_to_platdata()
198 		dev_read_u32_default(bus, "spi-activate-delay", 0);  in rockchip_spi_ofdata_to_platdata()
205 	return 0;  in rockchip_spi_ofdata_to_platdata()
260 	if (ret < 0) {  in rockchip_spi_probe()
269 	return 0;  in rockchip_spi_probe()
281 	rkspi_enable_chip(regs, 0);  in rockchip_spi_claim_bus()
309 	/* set SPI mode 0..3 */  in rockchip_spi_claim_bus()
331 	ctrlr0 |= 0 << RXDSD_SHIFT;  in rockchip_spi_claim_bus()
341 	return 0;  in rockchip_spi_claim_bus()
351 	return 0;  in rockchip_spi_release_bus()
376 	while (len > 0) {  in rockchip_spi_xfer()
377 		int todo = min(len, 0xffff);  in rockchip_spi_xfer()
389 				writel(out ? *out++ : 0, regs->txdr);  in rockchip_spi_xfer()
425 	return 0;  in rockchip_spi_set_speed()
434 	return 0;  in rockchip_spi_set_mode()