Lines Matching +full:disable +full:- +full:hi +full:- +full:speed
1 // SPDX-License-Identifier: GPL-2.0+
24 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_write_speed()
27 cadence_qspi_apb_config_baudrate_div(priv->regbase, in cadence_spi_write_speed()
30 /* Reconfigure delay timing if speed is changed. */ in cadence_spi_write_speed()
31 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
32 plat->tshsl_ns, plat->tsd2d_ns, in cadence_spi_write_speed()
33 plat->tchsh_ns, plat->tslch_ns); in cadence_spi_write_speed()
42 void *base = priv->regbase; in spi_calibration()
45 int err = 0, i, range_lo = -1, range_hi = -1; in spi_calibration()
67 /* Disable QSPI */ in spi_calibration()
85 if (range_lo == -1 && temp == idcode) { in spi_calibration()
90 /* search for range hi */ in spi_calibration()
91 if (range_lo != -1 && temp != idcode) { in spi_calibration()
92 range_hi = i - 1; in spi_calibration()
98 if (range_lo == -1) { in spi_calibration()
103 /* Disable QSPI for subsequent initialization */ in spi_calibration()
108 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", in spi_calibration()
111 /* just to ensure we do once only when speed or chip select change */ in spi_calibration()
112 priv->qspi_calibrated_hz = hz; in spi_calibration()
113 priv->qspi_calibrated_cs = spi_chip_select(bus); in spi_calibration()
120 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_set_speed()
124 if (hz > plat->max_hz) in cadence_spi_set_speed()
125 hz = plat->max_hz; in cadence_spi_set_speed()
127 /* Disable QSPI */ in cadence_spi_set_speed()
128 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_speed()
131 * Calibration required for different current SCLK speed, requested in cadence_spi_set_speed()
132 * SCLK speed or chip select in cadence_spi_set_speed()
134 if (priv->previous_hz != hz || in cadence_spi_set_speed()
135 priv->qspi_calibrated_hz != hz || in cadence_spi_set_speed()
136 priv->qspi_calibrated_cs != spi_chip_select(bus)) { in cadence_spi_set_speed()
142 priv->previous_hz = hz; in cadence_spi_set_speed()
146 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_speed()
148 debug("%s: speed=%d\n", __func__, hz); in cadence_spi_set_speed()
155 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_probe()
158 priv->regbase = plat->regbase; in cadence_spi_probe()
159 priv->ahbbase = plat->ahbbase; in cadence_spi_probe()
161 if (!priv->qspi_is_init) { in cadence_spi_probe()
163 priv->qspi_is_init = 1; in cadence_spi_probe()
173 /* Disable QSPI */ in cadence_spi_set_mode()
174 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_mode()
177 cadence_qspi_apb_set_clk_mode(priv->regbase, mode); in cadence_spi_set_mode()
180 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_mode()
188 struct udevice *bus = dev->parent; in cadence_spi_xfer()
189 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_xfer()
192 void *base = priv->regbase; in cadence_spi_xfer()
193 u8 *cmd_buf = priv->cmd_buf; in cadence_spi_xfer()
200 priv->cmd_len = bitlen / 8; in cadence_spi_xfer()
201 memcpy(cmd_buf, dout, priv->cmd_len); in cadence_spi_xfer()
214 plat->is_decoded_cs); in cadence_spi_xfer()
217 if (priv->cmd_len == 0) { in cadence_spi_xfer()
219 return -1; in cadence_spi_xfer()
225 if (!CQSPI_IS_ADDR(priv->cmd_len)) in cadence_spi_xfer()
231 if (!CQSPI_IS_ADDR(priv->cmd_len)) in cadence_spi_xfer()
240 base, priv->cmd_len, cmd_buf, in cadence_spi_xfer()
246 priv->cmd_len, cmd_buf, in cadence_spi_xfer()
251 priv->cmd_len, dm_plat->mode, cmd_buf); in cadence_spi_xfer()
259 (plat, priv->cmd_len, cmd_buf); in cadence_spi_xfer()
266 err = -1; in cadence_spi_xfer()
272 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); in cadence_spi_xfer()
273 priv->cmd_len = 0; in cadence_spi_xfer()
282 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_ofdata_to_platdata()
283 const void *blob = gd->fdt_blob; in cadence_spi_ofdata_to_platdata()
287 plat->regbase = (void *)devfdt_get_addr_index(bus, 0); in cadence_spi_ofdata_to_platdata()
288 plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); in cadence_spi_ofdata_to_platdata()
289 plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs"); in cadence_spi_ofdata_to_platdata()
290 plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128); in cadence_spi_ofdata_to_platdata()
291 plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4); in cadence_spi_ofdata_to_platdata()
292 plat->trigger_address = fdtdec_get_uint(blob, node, in cadence_spi_ofdata_to_platdata()
293 "cdns,trigger-address", 0); in cadence_spi_ofdata_to_platdata()
299 return -ENODEV; in cadence_spi_ofdata_to_platdata()
303 plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", in cadence_spi_ofdata_to_platdata()
307 plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256); in cadence_spi_ofdata_to_platdata()
308 plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16); in cadence_spi_ofdata_to_platdata()
309 plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200); in cadence_spi_ofdata_to_platdata()
310 plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255); in cadence_spi_ofdata_to_platdata()
311 plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20); in cadence_spi_ofdata_to_platdata()
312 plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20); in cadence_spi_ofdata_to_platdata()
314 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", in cadence_spi_ofdata_to_platdata()
315 __func__, plat->regbase, plat->ahbbase, plat->max_hz, in cadence_spi_ofdata_to_platdata()
316 plat->page_size); in cadence_spi_ofdata_to_platdata()
332 { .compatible = "cdns,qspi-nor" },