1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 	u8 reserved008[0x10 - 0x8];
20 	u8 reserved028[0x30 - 0x28];
24 	u8 reserved03c[0x50 - 0x3C];
31 	u8 reserved068[0xc0 - 0x68];
39 	u32 init3;		/* 0xdc SDRAM Initialization 3*/
45 	u8 reserved0f4[0x100 - 0xf4];
49 	u32 dramtmg3;		/* 0x10c SDRAM Timing 3*/
55 	u8 reserved124[0x138 - 0x124];
58 	u8 reserved140[0x180 - 0x140];
72 	u8 reserved1b4[0x1bc - 0x1b4];
74 	u8 reserved1c0[0x1c4 - 0x1c0];
76 	u8 reserved1c8[0x204 - 0x1c8];
79 	u32 addrmap3;		/* 0x20c Address Map 3*/
83 	u8 reserved21c[0x224 - 0x21c];
87 	u8 reserved230[0x240 - 0x230];
90 	u8 reserved248[0x250 - 0x248];
99 	u8 reserved27c[0x300 - 0x270];
105 	u8 reserved314[0x320 - 0x314];
108 	u8 reserved328[0x36c - 0x328];
111 	u8 reserved374[0x3fc - 0x374];
120 	u8 reserved40c[0x490 - 0x40c];
126 	u8 reserved4a4[0x4b4 - 0x4a4];
131 	u8 reserved4bc[0x540 - 0x4bc];
160 	u32 mr3;		/* 0x4C Mode 3*/
165 	u8 res1[0x0c0 - 0x060];	/* 0x60 */
174 	u8 res2[0x100 - 0xe0];	/* 0xe0 */
192 	u8 res3[0x178 - 0x144];	/* 0x144 */
199 	u8 res4[0x1C0 - 0x190];	/* 0x190 */
200 	u32 dx0gcr;		/* 0x1c0 Byte lane 0 General Configuration*/
201 	u32 dx0gsr0;		/* 0x1c4 Byte lane 0 General Status 0*/
202 	u32 dx0gsr1;		/* 0x1c8 Byte lane 0 General Status 1*/
203 	u32 dx0dllcr;		/* 0x1cc Byte lane 0 DLL Control*/
204 	u32 dx0dqtr;		/* 0x1d0 Byte lane 0 DQ Timing*/
205 	u32 dx0dqstr;		/* 0x1d4 Byte lane 0 DQS Timing*/
206 	u8 res5[0x200 - 0x1d8];	/* 0x1d8 */
207 	u32 dx1gcr;		/* 0x200 Byte lane 1 General Configuration*/
208 	u32 dx1gsr0;		/* 0x204 Byte lane 1 General Status 0*/
209 	u32 dx1gsr1;		/* 0x208 Byte lane 1 General Status 1*/
210 	u32 dx1dllcr;		/* 0x20c Byte lane 1 DLL Control*/
211 	u32 dx1dqtr;		/* 0x210 Byte lane 1 DQ Timing*/
212 	u32 dx1dqstr;		/* 0x214 Byte lane 1 QS Timing*/
213 	u8 res6[0x240 - 0x218];	/* 0x218 */
214 	u32 dx2gcr;		/* 0x240 Byte lane 2 General Configuration*/
215 	u32 dx2gsr0;		/* 0x244 Byte lane 2 General Status 0*/
216 	u32 dx2gsr1;		/* 0x248 Byte lane 2 General Status 1*/
217 	u32 dx2dllcr;		/* 0x24c Byte lane 2 DLL Control*/
218 	u32 dx2dqtr;		/* 0x250 Byte lane 2 DQ Timing*/
219 	u32 dx2dqstr;		/* 0x254 Byte lane 2 QS Timing*/
220 	u8 res7[0x280 - 0x258];	/* 0x258 */
221 	u32 dx3gcr;		/* 0x280 Byte lane 3 General Configuration*/
222 	u32 dx3gsr0;		/* 0x284 Byte lane 3 General Status 0*/
223 	u32 dx3gsr1;		/* 0x288 Byte lane 3 General Status 1*/
224 	u32 dx3dllcr;		/* 0x28c Byte lane 3 DLL Control*/
225 	u32 dx3dqtr;		/* 0x290 Byte lane 3 DQ Timing*/
226 	u32 dx3dqstr;		/* 0x294 Byte lane 3 QS Timing*/
229 #define DXN(phy, offset, byte)	((u32)(phy) + (offset) + ((u32)(byte) * 0x40))  argument
230 #define DXNGCR(phy, byte)	DXN(phy, 0x1c0, byte)  argument
231 #define DXNDLLCR(phy, byte)	DXN(phy, 0x1cc, byte)  argument
232 #define DXNDQTR(phy, byte)	DXN(phy, 0x1d0, byte)  argument
233 #define DXNDQSTR(phy, byte)	DXN(phy, 0x1d4, byte)  argument
245 #define DDRCTRL_STAT_OPERATING_MODE_SR		3
247 #define DDRCTRL_STAT_SELFREF_TYPE_ASR		(3 << 4)
303 #define DDRPHYC_PIR_ZCAL			BIT(3)
338 #define DDRPHYC_DXNDQTR_DQDLY_MASK		GENMASK(3, 0)
340 #define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK		GENMASK(3, 2)