Lines Matching +full:num +full:- +full:rx +full:- +full:queues
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
35 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
39 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
46 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
48 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
49 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
58 #define MACCFG2_PREL_SHIFT (31 - 19)
129 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
137 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
138 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
139 #define REMODER_RX_QOS_MODE_SHIFT (31-15)
142 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
150 /* BMRx - Bus Mode Register */
169 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
189 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
190 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
194 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
195 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
205 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
212 #define UESCR_MAXCOV_SHIFT (15 - 7)
213 #define UESCR_SCOV_SHIFT (15 - 15)
228 /* Send queue queue-descriptor, each Tx queue has one this QD
273 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
275 u8 res1[0x70-0x64];
299 u8 res0[0x38-0x02];
307 u8 res2[0x80-0x74];
311 /****** Rx data struct collection ******/
312 /* Rx thread data, each Rx thread has one this struct.
318 /* Rx thread parameter, each Rx thread has one this struct.
324 /* Rx firmware counters
351 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
362 /* RxBD queue entry, each Rx queue has one this entry.
371 /* Rx global paramter table
375 u32 rqptr; /* base pointer to the Rx Queues */
377 u8 res1[0x20-0xC];
380 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
381 u32 rxrmonbaseptr; /* Rx RMON statistics base */
382 u8 res3[0x30-0x28];
384 u8 res4[0x36-0x34];
386 u8 res5[0x46-0x37];
400 u8 res6[0x100-0xC4]; /* Initialize to zero */
407 /* UCC statistics - hardware counters
438 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
439 u8 res2[0x38 - 0x30];
445 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
446 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
477 u8 res0[0x40-0x38];
539 #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
540 #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
541 #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
542 #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
543 #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
544 #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
545 #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
546 #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
550 /* Rx Prefetched BDs
652 #define STD_UEC_INFO(num) \ argument
655 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
656 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
657 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
658 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
666 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
667 .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
668 .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
703 /* Rx and Tx paramter */
739 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);