Lines Matching +full:0 +full:x0541
17 /* Lane 0 */
21 { PHY_TYPE_UNCONNECTED, 0x0 },
22 { PHY_TYPE_SGMII1, 0x0 },
23 { PHY_TYPE_USB3_HOST0, 0x1 },
24 { PHY_TYPE_USB3_DEVICE, 0x1 }
31 { PHY_TYPE_UNCONNECTED, 0x0},
32 { PHY_TYPE_SGMII0, 0x0},
33 { PHY_TYPE_PEX0, 0x1}
40 { PHY_TYPE_UNCONNECTED, 0x0},
41 { PHY_TYPE_SATA0, 0x0},
42 { PHY_TYPE_USB3_HOST0, 0x1},
43 { PHY_TYPE_USB3_DEVICE, 0x1}
55 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
56 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
57 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
58 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
59 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
60 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
61 {0x104, 0x0C10}
66 /* 0 1 2 3 4 5 6 7 */
69 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
70 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
71 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
72 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
73 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
74 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
75 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
76 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
77 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
78 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
79 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
80 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
81 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
82 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
83 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
84 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
85 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
86 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
87 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
88 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
89 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
90 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
92 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
93 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
94 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
95 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
96 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
97 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
98 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
99 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
100 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
101 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
103 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
116 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
138 * return: 1 on success, 0 on timeout
142 u32 rval = 0xDEAD, timeout; in comphy_poll_reg()
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
157 return 0; in comphy_poll_reg()
163 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up()
200 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); in comphy_pcie_power_up()
205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); in comphy_pcie_power_up()
213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up()
223 0xFFFF); in comphy_pcie_power_up()
229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_pcie_power_up()
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); in reg_set_indirect()
272 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
281 * 0. Swap SATA TX lines in comphy_sata_power_up()
288 reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit); in comphy_sata_power_up()
295 reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF); in comphy_sata_power_up()
298 reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF); in comphy_sata_power_up()
309 reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin); in comphy_sata_power_up()
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); in comphy_sata_power_up()
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); in comphy_sata_power_up()
344 * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]) in usb3_reg_set16()
346 * offset is 0x200 in usb3_reg_set16()
359 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb3_power_up()
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); in comphy_usb3_power_up()
379 /* 0xd005c300 = 0x1001 */ in comphy_usb3_power_up()
381 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); in comphy_usb3_power_up()
387 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db in comphy_usb3_power_up()
388 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR in comphy_usb3_power_up()
397 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ in comphy_usb3_power_up()
398 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane); in comphy_usb3_power_up()
404 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane); in comphy_usb3_power_up()
408 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane); in comphy_usb3_power_up()
411 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane); in comphy_usb3_power_up()
417 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane); in comphy_usb3_power_up()
426 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); in comphy_usb3_power_up()
427 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); in comphy_usb3_power_up()
430 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); in comphy_usb3_power_up()
431 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane); in comphy_usb3_power_up()
437 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane); in comphy_usb3_power_up()
442 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane); in comphy_usb3_power_up()
447 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane); in comphy_usb3_power_up()
452 usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF, in comphy_usb3_power_up()
459 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); in comphy_usb3_power_up()
462 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); in comphy_usb3_power_up()
465 * 10. Set max speed generation to USB3.0 5Gbps in comphy_usb3_power_up()
467 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane); in comphy_usb3_power_up()
470 * 11. Set capacitor value for FFE gain peaking to 0xF in comphy_usb3_power_up()
472 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane); in comphy_usb3_power_up()
479 | 0x20, 0xFFFF, lane); in comphy_usb3_power_up()
488 0xFFFFFFFF); in comphy_usb3_power_up()
530 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
538 if (usb32 != 0 && usb32 != 1) { in comphy_usb2_power_up()
539 printf("invalid usb32 value: (%d), should be either 0 or 1\n", in comphy_usb2_power_up()
542 return 0; in comphy_usb2_power_up()
546 * 0. Setup PLL. 40MHz clock uses defaults. in comphy_usb2_power_up()
551 0x3F | (0xFF << 16) | (0x3 << 28)); in comphy_usb2_power_up()
558 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); in comphy_usb2_power_up()
560 if (usb32 != 0) { in comphy_usb2_power_up()
564 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb2_power_up()
569 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0, in comphy_usb2_power_up()
615 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
624 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); in comphy_emmc_power_up()
629 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); in comphy_emmc_power_up()
634 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); in comphy_emmc_power_up()
639 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0); in comphy_emmc_power_up()
644 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); in comphy_emmc_power_up()
645 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000); in comphy_emmc_power_up()
650 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); in comphy_emmc_power_up()
651 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0); in comphy_emmc_power_up()
669 fix_idx = 0; in comphy_sgmii_phy_init()
670 for (addr = 0; addr < 512; addr++) { in comphy_sgmii_phy_init()
688 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF); in comphy_sgmii_phy_init()
695 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
705 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 in comphy_sgmii_power_up()
708 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF); in comphy_sgmii_power_up()
714 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. in comphy_sgmii_power_up()
722 * 5. Release reset to the PHY by setting PIN_RESET=0. in comphy_sgmii_power_up()
724 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); in comphy_sgmii_power_up()
727 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide in comphy_sgmii_power_up()
732 (0x8 << rf_gen_rx_sel_shift) | in comphy_sgmii_power_up()
733 (0x8 << rf_gen_tx_sel_shift), in comphy_sgmii_power_up()
738 (0x6 << rf_gen_rx_sel_shift) | in comphy_sgmii_power_up()
739 (0x6 << rf_gen_tx_sel_shift), in comphy_sgmii_power_up()
743 return 0; in comphy_sgmii_power_up()
760 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel); in comphy_sgmii_power_up()
768 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); in comphy_sgmii_power_up()
772 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); in comphy_sgmii_power_up()
775 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ in comphy_sgmii_power_up()
788 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask); in comphy_sgmii_power_up()
792 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F in comphy_sgmii_power_up()
798 * specification DFE_UPDATE_EN already has the default value 0x3F in comphy_sgmii_power_up()
831 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); in comphy_sgmii_power_up()
834 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_sgmii_power_up()
858 * 21. Set COMPHY input port PIN_TX_IDLE=0 in comphy_sgmii_power_up()
860 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); in comphy_sgmii_power_up()
865 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE in comphy_sgmii_power_up()
866 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after in comphy_sgmii_power_up()
870 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); in comphy_sgmii_power_up()
882 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); in comphy_sgmii_power_up()
896 for (usb32 = 0; usb32 <= 1; usb32++) { in comphy_dedicated_phys_init()
901 if (usb32 == 0) { in comphy_dedicated_phys_init()
909 if (node > 0) { in comphy_dedicated_phys_init()
918 usb32 == 0 ? 2 : 3); in comphy_dedicated_phys_init()
921 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); in comphy_dedicated_phys_init()
927 if (node > 0) { in comphy_dedicated_phys_init()
943 if (node <= 0) { in comphy_dedicated_phys_init()
948 if (node > 0) { in comphy_dedicated_phys_init()
970 u32 lane, ret = 0; in comphy_a3700_init()
978 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; in comphy_a3700_init()
981 debug("Serdes type = 0x%x invert=%d\n", in comphy_a3700_init()