17 #define AQUNTIA_10G_CTL		0x20
18 #define AQUNTIA_VENDOR_P1	0xc400
20 #define AQUNTIA_SPEED_LSB_MASK	0x2000
21 #define AQUNTIA_SPEED_MSB_MASK	0x40
23 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
24 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
25 #define AQUANTIA_FIRMWARE_ID		 0x20
26 #define AQUANTIA_RESERVED_STATUS	 0xc885
27 #define AQUANTIA_FIRMWARE_MAJOR_MASK	 0xff00
28 #define AQUANTIA_FIRMWARE_MINOR_MASK	 0xff
29 #define AQUANTIA_FIRMWARE_BUILD_MASK	 0xf0
31 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
32 #define AQUANTIA_SI_IN_USE_MASK          0x0078
33 #define AQUANTIA_SI_USXGMII              0x0018
36 #define GLOBAL_FIRMWARE_ID 0x20
37 #define GLOBAL_FAULT 0xc850
38 #define GLOBAL_RSTATUS_1 0xc885
40 #define GLOBAL_STANDARD_CONTROL 0x0
44 #define MAILBOX_CONTROL 0x0200
50 #define MAILBOX_CRC 0x0201
52 #define MAILBOX_ADDR_MSW 0x0202
53 #define MAILBOX_ADDR_LSW 0x0203
55 #define MAILBOX_DATA_MSW 0x0204
56 #define MAILBOX_DATA_LSW 0x0205
58 #define UP_CONTROL 0xc001
61 #define UP_RUN_STALL BIT(0)
64 #define DRAM_BASE_ADDR 0x3FFE0000
65 #define IRAM_BASE_ADDR 0x40000000
68 #define VERSION_STRING_SIZE 0x40
69 #define VERSION_STRING_OFFSET 0x0200
70 #define HEADER_OFFSET 0x300
91 	*fw_length = 0;  in aquantia_read_fw()
95 	if (ret < 0)  in aquantia_read_fw()
99 	if (ret < 0)  in aquantia_read_fw()
109 	if (ret < 0)  in aquantia_read_fw()
112 	ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,  in aquantia_read_fw()
114 	if (ret < 0)  in aquantia_read_fw()
122 	if (ret < 0) {  in aquantia_read_fw()
136 	u16 crc = 0, up_crc;  in aquantia_load_memory()
140 	phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);  in aquantia_load_memory()
142 	for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {  in aquantia_load_memory()
143 		u32 word = 0;  in aquantia_load_memory()
150 			  word & 0xffff);  in aquantia_load_memory()
162 		printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",  in aquantia_load_memory()
166 	return 0;  in aquantia_load_memory()
171 	return (data[2] << 16) + (data[1] << 8) + data[0];  in unpack_u24()
178 	size_t fw_length = 0;  in aquantia_upload_firmware()
185 	if (ret != 0)  in aquantia_upload_firmware()
189 	calculated_crc = crc16_ccitt(0, addr, fw_length - 2);  in aquantia_upload_firmware()
191 		printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",  in aquantia_upload_firmware()
198 	primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;  in aquantia_upload_firmware()
219 	debug("loading dram 0x%08x from offset=%d size=%d\n",  in aquantia_upload_firmware()
223 	if (ret != 0)  in aquantia_upload_firmware()
226 	debug("loading iram 0x%08x from offset=%d size=%d\n",  in aquantia_upload_firmware()
230 	if (ret != 0)  in aquantia_upload_firmware()
234 	phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);  in aquantia_upload_firmware()
260 	u32 reg_val1 = 0;  in aquantia_config()
266 	if (id != 0)  in aquantia_config()
268 		       phydev->dev->name, (id >> 8), id & 0xff,  in aquantia_config()
269 		       (rstatus >> 4) & 0xf);  in aquantia_config()
271 	if (fault != 0)  in aquantia_config()
272 		printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);  in aquantia_config()
274 	if (id == 0 || fault != 0) {  in aquantia_config()
278 		if (ret != 0)  in aquantia_config()
322 		phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);  in aquantia_config()
341 	return 0;  in aquantia_config()
347 	int i = 0;  in aquantia_startup()
360 			if ((i++ % 500) == 0)  in aquantia_startup()
373 	if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))  in aquantia_startup()
374 		phydev->link = 0;  in aquantia_startup()
391 	return 0;  in aquantia_startup()
396 	.uid = 0x3a1b445,
397 	.mask = 0xfffffff0,
409 	.uid = 0x3a1b460,
410 	.mask = 0xfffffff0,
422 	.uid = 0x3a1b4a2,
423 	.mask = 0xfffffff0,
435 	.uid = 0x3a1b4d0,
436 	.mask = 0xfffffff0,
448 	.uid = 0x3a1b4e0,
449 	.mask = 0xfffffff0,
461 	.uid = 0x3a1b4b2,
462 	.mask = 0xfffffff0,
481 	return 0;  in phy_aquantia_init()