Lines Matching refs:pe
1405 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
1409 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1413 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1416 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1418 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1421 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1423 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1429 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1433 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1437 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1439 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1441 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1445 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1448 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1450 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1480 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
1484 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1485 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1489 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
1495 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1497 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1501 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
1507 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1508 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1509 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1513 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
1517 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1521 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
1525 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1526 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1530 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
1534 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1535 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1539 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
1542 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
1543 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
1547 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
1550 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1554 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
1557 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1561 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
1573 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1575 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1577 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
1582 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
1594 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1596 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1598 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
1603 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
1610 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1611 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1619 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
1624 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
1626 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
1632 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
1637 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1640 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1644 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1648 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
1650 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
1653 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
1659 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
1665 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1668 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1672 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1674 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); in mvpp2_prs_sram_offset_set()
1675 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1678 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1683 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
1685 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
1688 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1690 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); in mvpp2_prs_sram_offset_set()
1692 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1697 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1702 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
1708 struct mvpp2_prs_entry *pe; in mvpp2_prs_flow_find() local
1711 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_flow_find()
1712 if (!pe) in mvpp2_prs_flow_find()
1714 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_flow_find()
1724 pe->index = tid; in mvpp2_prs_flow_find()
1725 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_flow_find()
1726 bits = mvpp2_prs_sram_ai_get(pe); in mvpp2_prs_flow_find()
1730 return pe; in mvpp2_prs_flow_find()
1732 kfree(pe); in mvpp2_prs_flow_find()
1760 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
1764 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1765 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1768 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_drop_all_set()
1769 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1770 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1773 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
1776 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
1777 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
1780 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1783 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
1787 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1789 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1795 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
1801 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1802 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_promisc_set()
1805 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_promisc_set()
1806 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1807 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1810 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
1813 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, in mvpp2_prs_mac_promisc_set()
1817 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
1821 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
1824 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1828 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1830 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
1837 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_multi_set() local
1847 pe.index = index; in mvpp2_prs_mac_multi_set()
1848 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_multi_set()
1851 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_multi_set()
1852 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1853 pe.index = index; in mvpp2_prs_mac_multi_set()
1856 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_multi_set()
1859 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, in mvpp2_prs_mac_multi_set()
1863 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); in mvpp2_prs_mac_multi_set()
1866 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_multi_set()
1870 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_multi_set()
1873 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1877 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1879 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_multi_set()
1912 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1916 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_def_flow_init()
1917 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1918 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1921 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1924 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1925 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1928 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1929 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1936 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1938 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mh_init()
1940 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1941 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1942 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1944 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1947 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1950 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1951 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1959 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1961 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_init()
1964 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1965 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1967 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1969 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1970 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1973 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1976 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1977 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
1989 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
1998 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
1999 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2000 pe.index = tid; in mvpp2_prs_etype_init()
2002 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES); in mvpp2_prs_etype_init()
2004 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
2006 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
2007 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2011 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2012 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2013 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2014 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2016 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2024 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2025 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2026 pe.index = tid; in mvpp2_prs_etype_init()
2028 mvpp2_prs_match_etype(&pe, 0, PROT_ARP); in mvpp2_prs_etype_init()
2031 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2032 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2033 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2036 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2041 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2042 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2043 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2044 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2046 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2054 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2055 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2056 pe.index = tid; in mvpp2_prs_etype_init()
2058 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
2061 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2062 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2063 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2068 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2073 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2074 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2075 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2076 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2080 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2088 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2089 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2090 pe.index = tid; in mvpp2_prs_etype_init()
2092 mvpp2_prs_match_etype(&pe, 0, PROT_IP); in mvpp2_prs_etype_init()
2093 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2098 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
2099 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2102 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
2105 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2110 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2111 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2112 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2113 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2115 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2123 pe.index = tid; in mvpp2_prs_etype_init()
2126 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2127 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2129 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2134 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
2135 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
2136 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2140 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2141 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2142 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2143 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2145 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2153 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2154 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2155 pe.index = tid; in mvpp2_prs_etype_init()
2157 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6); in mvpp2_prs_etype_init()
2160 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
2163 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
2164 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2167 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2171 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2172 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2173 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2174 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2176 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2179 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2180 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2181 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
2184 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
2187 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2188 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2189 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2192 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2197 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2198 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2199 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2200 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2202 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2256 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2263 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2279 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_range_find() local
2282 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_range_find()
2283 if (!pe) in mvpp2_prs_mac_da_range_find()
2285 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_range_find()
2297 pe->index = tid; in mvpp2_prs_mac_da_range_find()
2298 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_mac_da_range_find()
2299 entry_pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_range_find()
2301 if (mvpp2_prs_mac_range_equals(pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2303 return pe; in mvpp2_prs_mac_da_range_find()
2305 kfree(pe); in mvpp2_prs_mac_da_range_find()
2314 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_accept() local
2320 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2324 if (!pe) { in mvpp2_prs_mac_da_accept()
2344 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_accept()
2345 if (!pe) in mvpp2_prs_mac_da_accept()
2347 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2348 pe->index = tid; in mvpp2_prs_mac_da_accept()
2351 mvpp2_prs_tcam_port_map_set(pe, 0); in mvpp2_prs_mac_da_accept()
2355 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2358 pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_accept()
2361 kfree(pe); in mvpp2_prs_mac_da_accept()
2364 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
2365 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
2366 kfree(pe); in mvpp2_prs_mac_da_accept()
2371 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
2376 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
2381 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2383 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2387 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
2391 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2392 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2393 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_mac_da_accept()
2395 kfree(pe); in mvpp2_prs_mac_da_accept()
2424 struct mvpp2_prs_entry *pe; in mvpp2_prs_def_flow() local
2427 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2430 if (!pe) { in mvpp2_prs_def_flow()
2438 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_def_flow()
2439 if (!pe) in mvpp2_prs_def_flow()
2442 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2443 pe->index = tid; in mvpp2_prs_def_flow()
2446 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2447 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2450 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2453 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2454 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2455 kfree(pe); in mvpp2_prs_def_flow()