Lines Matching +full:0 +full:x3e000000
13 #define PDMA_BASE 0x0800
14 #define GDMA1_BASE 0x0500
15 #define GDMA2_BASE 0x1500
16 #define GMAC_BASE 0x10000
20 #define ETHSYS_SYSCFG0_REG 0x14
22 #define SYSCFG0_GE_MODE_M 0x3
24 #define ETHSYS_CLKCFG0_REG 0x2c
28 #define GE_MODE_RGMII 0
36 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
37 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
38 #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
39 #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
41 #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
42 #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
43 #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
44 #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
46 #define PDMA_GLO_CFG_REG 0x204
51 #define TX_DMA_EN BIT(0)
53 #define PDMA_RST_IDX_REG 0x208
55 #define RST_DTX_IDX0 BIT(0)
58 #define GDMA_IG_CTRL_REG 0x000
64 #define MYMAC_DP_M 0xf000
66 #define BC_DP_M 0xf00
68 #define MC_DP_M 0xf0
69 #define UN_DP_S 0
70 #define UN_DP_M 0x0f
72 #define GDMA_MAC_LSB_REG 0x008
74 #define GDMA_MAC_MSB_REG 0x00c
77 #define DP_PDMA 0
86 #define GMAC_PIAC_REG 0x0004
89 #define MDIO_REG_ADDR_M 0x3e000000
91 #define MDIO_PHY_ADDR_M 0x1f00000
93 #define MDIO_CMD_M 0xc0000
95 #define MDIO_ST_M 0x30000
96 #define MDIO_RW_DATA_S 0
97 #define MDIO_RW_DATA_M 0xffff
100 #define MDIO_CMD_ADDR 0
106 #define MDIO_ST_C45 0
109 #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
111 #define MAC_RX_PKT_LEN_M 0x3000000
113 #define IPG_CFG_M 0xc0000
123 #define FORCE_SPD_M 0x0c
125 #define FORCE_LINK BIT(0)
128 #define MAC_RX_PKT_LEN_1518 0
134 #define SPEED_10M 0
138 #define GMAC_TRGMII_RCK_CTRL 0x300
142 #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
144 #define TD_DM_DRVN_M 0xf0
145 #define TD_DM_DRVP_S 0
146 #define TD_DM_DRVP_M 0x0f
150 #define PCR_REG(p) (0x2004 + (p) * 0x100)
152 #define PORT_MATRIX_M 0xff0000
154 #define PVC_REG(p) (0x2010 + (p) * 0x100)
156 #define STAG_VPID_M 0xffff0000
158 #define VLAN_ATTR_M 0xc0
161 #define VLAN_ATTR_USER 0
166 #define PCMR_REG(p) (0x3000 + (p) * 0x100)
169 #define SYS_CTRL_REG 0x7000
172 #define SW_REG_RST BIT(0)
176 #define HWTRAP_REG 0x7800
177 #define MHWTRAP_REG 0x7804
181 #define P5_INTF_SEL_M 0x2000
183 #define SMI_ADDR_M 0x1800
185 #define XTAL_FSEL_M 0x600
188 #define P5_INTF_MODE_M 0x80
191 #define CHIP_MODE_S 0
192 #define CHIP_MODE_M 0x0f
195 #define P5_INTF_SEL_GPHY 0
199 #define P5_INTF_MODE_GMII_MII 0
202 #define MT7530_P6ECR 0x7830
203 #define P6_INTF_MODE_M 0x3
204 #define P6_INTF_MODE_S 0
207 #define P6_INTF_MODE_RGMII 0
210 #define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
211 #define RD_TAP_S 0
212 #define RD_TAP_M 0x7f
214 #define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
219 #define MII_MMD_ACC_CTL_REG 0x0d
221 #define MMD_CMD_M 0xc000
222 #define MMD_DEVAD_S 0
223 #define MMD_DEVAD_M 0x1f
226 #define MMD_ADDR 0
231 #define MII_MMD_ADDR_DATA_REG 0x0e
235 #define CORE_PLL_GROUP2 0x401
239 #define RG_SYSPLL_POSDIV_M 0x60
241 #define CORE_PLL_GROUP4 0x403
246 #define CORE_PLL_GROUP5 0x404
247 #define RG_LCDDS_PCW_NCPO1_S 0
248 #define RG_LCDDS_PCW_NCPO1_M 0xffff
250 #define CORE_PLL_GROUP6 0x405
251 #define RG_LCDDS_PCW_NCPO0_S 0
252 #define RG_LCDDS_PCW_NCPO0_M 0xffff
254 #define CORE_PLL_GROUP7 0x406
258 #define RG_LCCDS_C_M 0x70
261 #define CORE_PLL_GROUP10 0x409
262 #define RG_LCDDS_SSC_DELTA_S 0
263 #define RG_LCDDS_SSC_DELTA_M 0xfff
265 #define CORE_PLL_GROUP11 0x40a
266 #define RG_LCDDS_SSC_DELTA1_S 0
267 #define RG_LCDDS_SSC_DELTA1_M 0xfff
269 #define CORE_GSWPLL_GRP1 0x40d
271 #define RG_GSWPLL_POSDIV_200M_M 0x3000
273 #define RG_GSWPLL_FBKDIV_200M_S 0
274 #define RG_GSWPLL_FBKDIV_200M_M 0xff
276 #define CORE_GSWPLL_GRP2 0x40e
278 #define RG_GSWPLL_POSDIV_500M_M 0x300
279 #define RG_GSWPLL_FBKDIV_500M_S 0
280 #define RG_GSWPLL_FBKDIV_500M_M 0xff
282 #define CORE_TRGMII_GSW_CLK_CG 0x410
283 #define REG_GSWCK_EN BIT(0)