Lines Matching +full:tuning +full:- +full:start +full:- +full:tap
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-direction.h>
18 #include "tmio-common.h"
116 bool hs400 = (mmc->selected_mode == MMC_HS_400); in renesas_sdhi_hs400()
117 int ret, taps = hs400 ? priv->nrtaps : 8; in renesas_sdhi_hs400()
120 if (taps == 4) /* HS400 on 4tap SoC needs different clock */ in renesas_sdhi_hs400()
121 ret = clk_set_rate(&priv->clk, 400000000); in renesas_sdhi_hs400()
123 ret = clk_set_rate(&priv->clk, 200000000); in renesas_sdhi_hs400()
145 tmio_sd_writel(priv, priv->tap_set >> 1, in renesas_sdhi_hs400()
148 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); in renesas_sdhi_hs400()
166 unsigned long tap) in renesas_sdhi_prepare_tuning() argument
169 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET); in renesas_sdhi_prepare_tuning()
182 unsigned long tap_cnt; /* counter of tuning success */ in renesas_sdhi_select_tuning()
183 unsigned long tap_start;/* start position of tuning success */ in renesas_sdhi_select_tuning()
184 unsigned long tap_end; /* end position of tuning success */ in renesas_sdhi_select_tuning()
185 unsigned long ntap; /* temporary counter of tuning success */ in renesas_sdhi_select_tuning()
209 * center index as the tap. in renesas_sdhi_select_tuning()
220 tap_start = i - ntap; in renesas_sdhi_select_tuning()
221 tap_end = i - 1; in renesas_sdhi_select_tuning()
229 tap_start = i - ntap; in renesas_sdhi_select_tuning()
230 tap_end = i - 1; in renesas_sdhi_select_tuning()
235 * If all of the TAP is OK, the sampling clock position is selected by in renesas_sdhi_select_tuning()
248 tap_start = i - ntap; in renesas_sdhi_select_tuning()
249 tap_end = i - 1; in renesas_sdhi_select_tuning()
256 tap_start = i - ntap; in renesas_sdhi_select_tuning()
257 tap_end = i - 1; in renesas_sdhi_select_tuning()
266 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; in renesas_sdhi_select_tuning()
268 return -EIO; in renesas_sdhi_select_tuning()
271 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); in renesas_sdhi_select_tuning()
273 /* Enable auto re-tuning */ in renesas_sdhi_select_tuning()
285 struct mmc *mmc = upriv->mmc; in renesas_sdhi_execute_tuning()
292 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) in renesas_sdhi_execute_tuning()
293 return -EINVAL; in renesas_sdhi_execute_tuning()
295 /* clock tuning is not needed for upto 52MHz */ in renesas_sdhi_execute_tuning()
296 if (!((mmc->selected_mode == MMC_HS_200) || in renesas_sdhi_execute_tuning()
297 (mmc->selected_mode == MMC_HS_400) || in renesas_sdhi_execute_tuning()
298 (mmc->selected_mode == UHS_SDR104) || in renesas_sdhi_execute_tuning()
299 (mmc->selected_mode == UHS_SDR50))) in renesas_sdhi_execute_tuning()
304 /* Tuning is not supported */ in renesas_sdhi_execute_tuning()
309 … "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); in renesas_sdhi_execute_tuning()
313 /* Issue CMD19 twice for each tap */ in renesas_sdhi_execute_tuning()
317 /* Force PIO for the tuning */ in renesas_sdhi_execute_tuning()
318 caps = priv->caps; in renesas_sdhi_execute_tuning()
319 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL; in renesas_sdhi_execute_tuning()
323 priv->caps = caps; in renesas_sdhi_execute_tuning()
339 dev_warn(dev, "Tuning procedure failed\n"); in renesas_sdhi_execute_tuning()
375 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && in renesas_sdhi_set_ios()
376 (mmc->selected_mode != UHS_SDR104) && in renesas_sdhi_set_ios()
377 (mmc->selected_mode != MMC_HS_200) && in renesas_sdhi_set_ios()
378 (mmc->selected_mode != MMC_HS_400)) { in renesas_sdhi_set_ios()
389 int ret = -ETIMEDOUT; in renesas_sdhi_wait_dat0()
395 while (timeout--) { in renesas_sdhi_wait_dat0()
427 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
428 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
429 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
430 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
431 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
432 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
433 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
434 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
435 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
436 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
437 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
443 return clk_get_rate(&priv->clk); in renesas_sdhi_clk_get_rate()
451 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) in renesas_sdhi_filter_caps()
460 plat->cfg.host_caps &= ~MMC_MODE_HS400; in renesas_sdhi_filter_caps()
462 /* H3 ES2.0 uses 4 tuning taps */ in renesas_sdhi_filter_caps()
465 priv->nrtaps = 4; in renesas_sdhi_filter_caps()
467 priv->nrtaps = 8; in renesas_sdhi_filter_caps()
475 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD; in renesas_sdhi_filter_caps()
477 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; in renesas_sdhi_filter_caps()
488 priv->clk_get_rate = renesas_sdhi_clk_get_rate; in renesas_sdhi_probe()
491 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), in renesas_sdhi_probe()
503 ret = clk_get_by_index(dev, 0, &priv->clk); in renesas_sdhi_probe()
510 ret = clk_set_rate(&priv->clk, 200000000); in renesas_sdhi_probe()
513 clk_free(&priv->clk); in renesas_sdhi_probe()
517 ret = clk_enable(&priv->clk); in renesas_sdhi_probe()
530 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS)) in renesas_sdhi_probe()
537 .name = "renesas-sdhi",