Lines Matching refs:bit_per_gpio
26 u8 bit_per_gpio; member
32 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_set_value()
35 reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift); in hsdk_creg_gpio_set_value()
65 val >>= oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_get_value()
66 val &= GENMASK(hcg->bit_per_gpio - 1, 0); in hsdk_creg_gpio_get_value()
81 u32 shift, bit_per_gpio, activate, deactivate, gpio_count; in hsdk_creg_gpio_probe() local
87 bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1); in hsdk_creg_gpio_probe()
96 if (!bit_per_gpio) { in hsdk_creg_gpio_probe()
110 if ((gpio_count * bit_per_gpio + shift) > 32) { in hsdk_creg_gpio_probe()
112 uc_priv->bank_name, gpio_count * bit_per_gpio + shift); in hsdk_creg_gpio_probe()
117 if (GENMASK(31, bit_per_gpio) & activate) { in hsdk_creg_gpio_probe()
119 uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0)); in hsdk_creg_gpio_probe()
124 if (GENMASK(31, bit_per_gpio) & deactivate) { in hsdk_creg_gpio_probe()
126 uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0)); in hsdk_creg_gpio_probe()
139 hcg->bit_per_gpio = (u8)bit_per_gpio; in hsdk_creg_gpio_probe()