Lines Matching full:cs
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
127 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", in ddr3_read_leveling_hw()
128 (u32) cs, 1); in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
201 /* Loop for each CS */ in ddr3_read_leveling_sw()
202 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
203 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()
221 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
223 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
229 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
233 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
237 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
241 /* Read leveling Single CS[cs] */ in ddr3_read_leveling_sw()
244 ddr3_read_leveling_single_cs_rl_mode(cs, freq, in ddr3_read_leveling_sw()
252 ddr3_read_leveling_single_cs_window_mode(cs, freq, in ddr3_read_leveling_sw()
262 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", (u32) cs, in ddr3_read_leveling_sw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
326 DEBUG_RL_S("DDR3 - Read Leveling - Finished RL procedure for all CS\n"); in ddr3_read_leveling_sw()
335 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun() argument
347 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
350 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
353 info->rl_val[cs][idx][C]++; in overrun()
356 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
362 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
392 * Args: cs - current chip select
399 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_rl_mode() argument
409 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_rl_mode()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
456 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_rl_mode()
470 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
483 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
578 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
619 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
622 cs)); in ddr3_read_leveling_single_cs_rl_mode()
668 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
670 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
680 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
681 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
724 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
725 reg |= ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
729 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
731 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
744 * Args: cs - current chip select
751 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_window_mode() argument
761 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_window_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
810 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_window_mode()
833 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
846 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
849 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
856 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
863 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
869 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
872 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
874 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
877 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
879 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
910 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_window_mode()
1024 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1027 cs)); in ddr3_read_leveling_single_cs_window_mode()
1070 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1072 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1083 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1084 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1097 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1099 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1101 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1110 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1111 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1112 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1113 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1115 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1116 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1117 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1118 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1128 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1132 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1134 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1143 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1148 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1149 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1150 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1151 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1157 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1167 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1198 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1200 ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1204 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_window_mode()
1206 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
1207 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()