Lines Matching refs:if_id
94 u32 if_id, u32 cl_value, u32 cwl_value);
102 u32 if_id, enum mv_ddr_freq frequency);
104 u32 if_id, enum mv_ddr_freq frequency);
228 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
286 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
289 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
292 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
296 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
303 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
309 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
318 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
324 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
337 u32 if_id; in hws_ddr3_tip_init_controller() local
363 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
364 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
366 ("active IF %d\n", if_id)); in hws_ddr3_tip_init_controller()
373 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
380 if_id, DUAL_DUNIT_CFG_REG, 0, in hws_ddr3_tip_init_controller()
385 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
399 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
405 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
410 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
415 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
426 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
431 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
439 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
443 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
449 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
455 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
473 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
482 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
487 if_id, cs_mask)); in hws_ddr3_tip_init_controller()
495 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt, in hws_ddr3_tip_init_controller()
511 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
514 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
528 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
532 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
553 ((tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
558 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
564 ddr3_tip_write_odt(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
566 ddr3_tip_set_timing(dev_num, access_type, if_id, freq); in hws_ddr3_tip_init_controller()
570 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
575 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
586 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
590 timing = tm->interface_params[if_id].timing; in hws_ddr3_tip_init_controller()
603 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
607 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
610 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
616 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
620 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
623 (data_read[if_id] == 0) ? (1 << 11) : 0; in hws_ddr3_tip_init_controller()
625 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
637 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
641 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
647 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
648 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
649 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id)); in hws_ddr3_tip_init_controller()
656 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
659 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
676 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev2_rank_control() argument
684 data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
687 if (tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
693 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
695 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
700 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
702 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
707 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
709 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
714 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
716 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
724 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev2_rank_control()
730 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev3_rank_control() argument
738 if ((tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
740 tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
742 (tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
744 tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
751 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
753 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
757 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev3_rank_control()
763 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rank_control() argument
766 return ddr3_tip_rev2_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
768 return ddr3_tip_rev3_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
992 u32 if_id, u32 reg_addr, u32 data_value, u32 mask) in ddr3_tip_if_write() argument
1003 u32 if_id, u32 reg_addr, u32 *data, u32 mask) in ddr3_tip_if_read() argument
1014 u32 if_id, u32 exp_value, u32 mask, u32 offset, in ddr3_tip_if_polling() argument
1027 start_if = if_id; in ddr3_tip_if_polling()
1028 end_if = if_id; in ddr3_tip_if_polling()
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read() argument
1077 u32 if_id, enum hws_access_type phy_access, in ddr3_tip_bus_write() argument
1094 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1105 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_read_modify_write()
1106 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_read_modify_write()
1108 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id, in ddr3_tip_bus_read_modify_write()
1112 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read_modify_write()
1124 u32 if_id, enum mv_ddr_freq frequency) in adll_calibration() argument
1133 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1137 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1147 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1151 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1158 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1162 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1169 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1173 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1177 if (ddr3_tip_if_polling(dev_num, access_type, if_id, in adll_calibration()
1186 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1190 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1197 u32 if_id, enum mv_ddr_freq frequency) in ddr3_tip_freq_set() argument
1215 enum mv_ddr_timing timing = tm->interface_params[if_id].timing; in ddr3_tip_freq_set()
1220 access_type, if_id, frequency)); in ddr3_tip_freq_set()
1228 start_if = if_id; in ddr3_tip_freq_set()
1229 end_if = if_id; in ddr3_tip_freq_set()
1234 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1236 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1237 cs_mask[if_id] = CS_BIT_MASK; in ddr3_tip_freq_set()
1238 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_freq_set()
1239 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1240 &cs_mask[if_id]); in ddr3_tip_freq_set()
1248 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_freq_set()
1249 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1251 flow_result[if_id] = TEST_SUCCESS; in ddr3_tip_freq_set()
1253 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_freq_set()
1254 if (tm->interface_params[if_id].memory_freq == in ddr3_tip_freq_set()
1257 tm->interface_params[if_id].cas_l; in ddr3_tip_freq_set()
1259 tm->interface_params[if_id].cas_wl; in ddr3_tip_freq_set()
1279 dev_num, access_type, if_id, in ddr3_tip_freq_set()
1293 tm->interface_params[if_id]. in ddr3_tip_freq_set()
1300 if_id, in ddr3_tip_freq_set()
1307 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1311 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1316 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1320 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1326 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1329 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1332 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1335 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1341 (dev_num, access_type, if_id, DFS_REG, 0x4, in ddr3_tip_freq_set()
1345 if_id, 0x8, 0x8, DFS_REG, in ddr3_tip_freq_set()
1368 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1374 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1378 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_freq_set()
1382 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
1387 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1390 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1399 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1405 (dev_num, access_type, if_id, 0x1874, in ddr3_tip_freq_set()
1408 (dev_num, access_type, if_id, 0x1884, in ddr3_tip_freq_set()
1411 (dev_num, access_type, if_id, 0x1894, in ddr3_tip_freq_set()
1414 (dev_num, access_type, if_id, 0x18a4, in ddr3_tip_freq_set()
1420 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1424 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1438 if_id, bus_cnt, DDR_PHY_DATA, in ddr3_tip_freq_set()
1445 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_freq_set()
1452 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1457 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1463 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff, in ddr3_tip_freq_set()
1472 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1476 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1480 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency); in ddr3_tip_freq_set()
1488 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1491 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG, in ddr3_tip_freq_set()
1499 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1502 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, in ddr3_tip_freq_set()
1510 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1514 (dev_num, access_type, if_id, DUNIT_MMASK_REG, in ddr3_tip_freq_set()
1522 (dev_num, access_type, if_id, MR0_REG, in ddr3_tip_freq_set()
1534 if_id, MR2_REG, in ddr3_tip_freq_set()
1542 if_id, DDR_ODT_TIMING_LOW_REG, in ddr3_tip_freq_set()
1546 if_id, DDR_ODT_TIMING_HIGH_REG, in ddr3_tip_freq_set()
1553 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf)); in ddr3_tip_freq_set()
1556 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, in ddr3_tip_freq_set()
1574 if_id, in ddr3_tip_freq_set()
1587 u32 if_id, u32 cl_value, u32 cwl_value) in ddr3_tip_write_odt() argument
1597 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1600 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1604 if_id, in ddr3_tip_write_odt()
1610 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1620 u32 if_id, enum mv_ddr_freq frequency) in ddr3_tip_set_timing() argument
1633 speed_bin_index = tm->interface_params[if_id].speed_bin_index; in ddr3_tip_set_timing()
1634 memory_size = tm->interface_params[if_id].memory_size; in ddr3_tip_set_timing()
1635 page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size); in ddr3_tip_set_timing()
1640 t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW; in ddr3_tip_set_timing()
1712 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1739 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1742 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1746 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1750 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG, in ddr3_tip_set_timing()
1766 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; in ddr3_tip_write_cs_result() local
1770 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1771 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_cs_result()
1776 tm->interface_params[if_id]. in ddr3_tip_write_cs_result()
1780 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_write_cs_result()
1788 if_id, in ddr3_tip_write_cs_result()
1806 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1811 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1812 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1814 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_mrs_cmd()
1816 (cs_mask_arr[if_id] << 8) | mr_data[mr_num].cmd, 0xf1f)); in ddr3_tip_write_mrs_cmd()
1819 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1820 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1821 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_write_mrs_cmd()
1837 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1841 if_id, 0x15c8, 0, 0xff000000)); in ddr3_tip_reset_fifo_ptr()
1847 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1851 if_id, 0x15b0, in ddr3_tip_reset_fifo_ptr()
1855 if_id, 0x1400, 0, 0x40000000)); in ddr3_tip_reset_fifo_ptr()
1858 if_id, 0x1400, in ddr3_tip_reset_fifo_ptr()
1862 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1866 if_id, 0x15b4, 0x10000, 0x10000)); in ddr3_tip_reset_fifo_ptr()
1876 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1880 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
1881 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_reset_phy_regs()
1887 if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_ddr3_reset_phy_regs()
1892 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1897 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1901 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1905 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1909 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1913 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1917 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1921 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1925 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1978 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
1982 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_adll_regs_bypass()
1983 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_adll_regs_bypass()
1987 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
1991 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
2011 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2034 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_ddr3_training_main_flow()
2035 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_training_main_flow()
2037 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2474 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2479 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2481 training_result[stage][if_id] = NO_TEST_DONE; in ddr3_tip_ddr3_auto_tune()
2504 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2507 if (training_result[stage][if_id] == TEST_FAILED) in ddr3_tip_ddr3_auto_tune()
2514 if_id)); in ddr3_tip_ddr3_auto_tune()
2543 u32 if_id = 0, mem_mask = 0, bus_index = 0; in ddr3_tip_enable_init_sequence() local
2551 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_enable_init_sequence()
2552 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_enable_init_sequence()
2555 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1, in ddr3_tip_enable_init_sequence()
2560 if_id)); in ddr3_tip_enable_init_sequence()
2570 tm->interface_params[if_id]. in ddr3_tip_enable_init_sequence()
2578 if_id, DUAL_DUNIT_CFG_REG, 1 << 3, in ddr3_tip_enable_init_sequence()
2661 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width() argument
2665 return (tm->interface_params[if_id].bus_width == in hws_ddr3_get_device_width()
2669 u32 hws_ddr3_get_device_size(u32 if_id) in hws_ddr3_get_device_size() argument
2673 if (tm->interface_params[if_id].memory_size >= in hws_ddr3_get_device_size()
2677 tm->interface_params[if_id].memory_size)); in hws_ddr3_get_device_size()
2680 return 1 << tm->interface_params[if_id].memory_size; in hws_ddr3_get_device_size()
2684 int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size) in hws_ddr3_calc_mem_cs_size() argument
2688 dev_size = hws_ddr3_get_device_size(if_id); in hws_ddr3_calc_mem_cs_size()
2691 hws_ddr3_get_device_width(if_id)) * dev_size); in hws_ddr3_calc_mem_cs_size()
2716 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr) in hws_ddr3_cs_base_adr_calc() argument
2724 if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK) in hws_ddr3_cs_base_adr_calc()
2747 hws_ddr3_get_device_width(if_id)); in hws_ddr3_cs_base_adr_calc()