Lines Matching +full:div +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
31 u8 div; member
50 if (!(*table).div) in gen2_clk_get_sdh_div()
54 return (*table).div; in gen2_clk_get_sdh_div()
60 static int gen2_clk_enable(struct clk *clk) in gen2_clk_enable() argument
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
64 return renesas_clk_endisable(clk, priv->base, true); in gen2_clk_enable()
67 static int gen2_clk_disable(struct clk *clk) in gen2_clk_disable() argument
69 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_disable()
71 return renesas_clk_endisable(clk, priv->base, false); in gen2_clk_disable()
74 static ulong gen2_clk_get_rate(struct clk *clk) in gen2_clk_get_rate() argument
76 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_get_rate()
77 struct cpg_mssr_info *info = priv->info; in gen2_clk_get_rate()
78 struct clk parent; in gen2_clk_get_rate()
81 priv->cpg_pll_config; in gen2_clk_get_rate()
82 u32 value, mult, div, rate = 0; in gen2_clk_get_rate() local
85 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); in gen2_clk_get_rate()
87 ret = renesas_clk_get_parent(clk, info, &parent); in gen2_clk_get_rate()
93 if (renesas_clk_is_mod(clk)) { in gen2_clk_get_rate()
95 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", in gen2_clk_get_rate()
100 ret = renesas_clk_get_core(clk, info, &core); in gen2_clk_get_rate()
104 switch (core->type) { in gen2_clk_get_rate()
106 if (core->id == info->clk_extal_id) { in gen2_clk_get_rate()
107 rate = clk_get_rate(&priv->clk_extal); in gen2_clk_get_rate()
108 debug("%s[%i] EXTAL clk: rate=%u\n", in gen2_clk_get_rate()
113 if (core->id == info->clk_extal_usb_id) { in gen2_clk_get_rate()
114 rate = clk_get_rate(&priv->clk_extal_usb); in gen2_clk_get_rate()
115 debug("%s[%i] EXTALR clk: rate=%u\n", in gen2_clk_get_rate()
120 return -EINVAL; in gen2_clk_get_rate()
123 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; in gen2_clk_get_rate()
124 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", in gen2_clk_get_rate()
126 core->parent, core->mult, core->div, rate); in gen2_clk_get_rate()
130 value = (readl(priv->base + core->offset) & 0x3f) + 1; in gen2_clk_get_rate()
132 debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n", in gen2_clk_get_rate()
134 core->parent, value, rate); in gen2_clk_get_rate()
138 rate = gen2_clk_get_rate(&parent) / pll_config->extal_div; in gen2_clk_get_rate()
139 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", in gen2_clk_get_rate()
141 core->parent, pll_config->extal_div, rate); in gen2_clk_get_rate()
146 * PLL0 is a configurable multiplier clock except on R-Car in gen2_clk_get_rate()
151 mult = pll_config->pll0_mult; in gen2_clk_get_rate()
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
157 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; in gen2_clk_get_rate()
158 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", in gen2_clk_get_rate()
159 __func__, __LINE__, core->parent, mult, rate); in gen2_clk_get_rate()
163 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2; in gen2_clk_get_rate()
164 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", in gen2_clk_get_rate()
166 core->parent, pll_config->pll1_mult, rate); in gen2_clk_get_rate()
170 rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult; in gen2_clk_get_rate()
171 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", in gen2_clk_get_rate()
173 core->parent, pll_config->pll3_mult, rate); in gen2_clk_get_rate()
177 value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf; in gen2_clk_get_rate()
178 div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value); in gen2_clk_get_rate()
179 rate = gen2_clk_get_rate(&parent) / div; in gen2_clk_get_rate()
180 debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n", in gen2_clk_get_rate()
182 core->parent, div, rate); in gen2_clk_get_rate()
186 value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf; in gen2_clk_get_rate()
187 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value); in gen2_clk_get_rate()
188 rate = gen2_clk_get_rate(&parent) / div; in gen2_clk_get_rate()
189 debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n", in gen2_clk_get_rate()
191 core->parent, div, rate); in gen2_clk_get_rate()
195 value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf; in gen2_clk_get_rate()
196 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value); in gen2_clk_get_rate()
197 rate = gen2_clk_get_rate(&parent) / div; in gen2_clk_get_rate()
198 debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n", in gen2_clk_get_rate()
200 core->parent, div, rate); in gen2_clk_get_rate()
206 return -ENOENT; in gen2_clk_get_rate()
209 static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate) in gen2_clk_setup_mmcif_div() argument
211 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_setup_mmcif_div()
212 struct cpg_mssr_info *info = priv->info; in gen2_clk_setup_mmcif_div()
214 struct clk parent, pparent; in gen2_clk_setup_mmcif_div()
218 ret = renesas_clk_get_parent(clk, info, &parent); in gen2_clk_setup_mmcif_div()
231 if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1")) in gen2_clk_setup_mmcif_div()
240 val = (gen2_clk_get_rate(&pparent) / rate) - 1; in gen2_clk_setup_mmcif_div()
242 debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset); in gen2_clk_setup_mmcif_div()
244 writel(val, priv->base + core->offset); in gen2_clk_setup_mmcif_div()
249 static ulong gen2_clk_set_rate(struct clk *clk, ulong rate) in gen2_clk_set_rate() argument
251 /* Force correct MMC-IF divider configuration if applicable */ in gen2_clk_set_rate()
252 gen2_clk_setup_mmcif_div(clk, rate); in gen2_clk_set_rate()
253 return gen2_clk_get_rate(clk); in gen2_clk_set_rate()
256 static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) in gen2_clk_of_xlate() argument
258 if (args->args_count != 2) { in gen2_clk_of_xlate()
259 debug("Invaild args_count: %d\n", args->args_count); in gen2_clk_of_xlate()
260 return -EINVAL; in gen2_clk_of_xlate()
263 clk->id = (args->args[0] << 16) | args->args[1]; in gen2_clk_of_xlate()
285 priv->base = (struct gen2_base *)devfdt_get_addr(dev); in gen2_clk_probe()
286 if (!priv->base) in gen2_clk_probe()
287 return -EINVAL; in gen2_clk_probe()
289 priv->info = info; in gen2_clk_probe()
290 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node); in gen2_clk_probe()
294 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); in gen2_clk_probe()
296 return -EINVAL; in gen2_clk_probe()
300 priv->cpg_pll_config = in gen2_clk_probe()
301 (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode); in gen2_clk_probe()
302 if (!priv->cpg_pll_config->extal_div) in gen2_clk_probe()
303 return -EINVAL; in gen2_clk_probe()
305 ret = clk_get_by_name(dev, "extal", &priv->clk_extal); in gen2_clk_probe()
309 if (info->extal_usb_node) { in gen2_clk_probe()
310 ret = clk_get_by_name(dev, info->extal_usb_node, in gen2_clk_probe()
311 &priv->clk_extal_usb); in gen2_clk_probe()
323 return renesas_clk_remove(priv->base, priv->info); in gen2_clk_remove()