1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch-owl/clk_s900.h>
12 #include <asm/arch-owl/regs_s900.h>
15 #include <dt-bindings/clock/s900_cmu.h>
22 	setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));  in owl_clk_init()
26 	/* Source HOSC to DEV_CLK */  in owl_clk_init()
27 	clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);  in owl_clk_init()
33 	writel(bus_clk, priv->base + CMU_BUSCLK);  in owl_clk_init()
38 	core_pll = readl(priv->base + CMU_COREPLL);  in owl_clk_init()
40 	writel(core_pll, priv->base + CMU_COREPLL);  in owl_clk_init()
45 	dev_pll = readl(priv->base + CMU_DEVPLL);  in owl_clk_init()
47 	writel(dev_pll, priv->base + CMU_DEVPLL);  in owl_clk_init()
51 	/* Source CORE_PLL for CORE_CLK */  in owl_clk_init()
52 	clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,  in owl_clk_init()
55 	/* Source DEV_PLL for DEV_CLK */  in owl_clk_init()
56 	setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);  in owl_clk_init()
63 	/* Source HOSC for UART5 interface */  in owl_uart_clk_enable()
64 	clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);  in owl_uart_clk_enable()
67 	setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);  in owl_uart_clk_enable()
73 	clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);  in owl_uart_clk_disable()
76 int owl_clk_enable(struct clk *clk)  in owl_clk_enable()  argument
78 	struct owl_clk_priv *priv = dev_get_priv(clk->dev);  in owl_clk_enable()
80 	switch (clk->id) {  in owl_clk_enable()
91 int owl_clk_disable(struct clk *clk)  in owl_clk_disable()  argument
93 	struct owl_clk_priv *priv = dev_get_priv(clk->dev);  in owl_clk_disable()
95 	switch (clk->id) {  in owl_clk_disable()
110 	priv->base = dev_read_addr(dev);  in owl_clk_probe()
111 	if (priv->base == FDT_ADDR_T_NONE)  in owl_clk_probe()
112 		return -EINVAL;  in owl_clk_probe()
126 	{ .compatible = "actions,s900-cmu" },