drivers/clk/clk_stm32h7.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32h7-clks.h>
120 	u32 cr;		/* 0x00 Source Control Register */
121 	u32 icscr;	/* 0x04 Internal Clock Source Calibration Register */
130 	u32 pllckselr;	/* 0x28 PLLs Clock Source Selection Register */
144 	u32 cier;	/* 0x60 Clock Source Interrupt Enable Register */
145 	u32 cifr;	/* 0x64 Clock Source Interrupt Flag Register */
146 	u32 cicr;	/* 0x68 Clock Source Interrupt Clear Register */
348 	struct stm32_rcc_regs *regs = priv->rcc_base;  in configure_clocks()
349 	uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);  in configure_clocks()
355 	setbits_le32(&regs->cr, RCC_CR_HSION);  in configure_clocks()
356 	while (!(readl(&regs->cr) & RCC_CR_HSIRDY))  in configure_clocks()
360 	writel(0, &regs->cfgr);  in configure_clocks()
363 	writel(0x0, &regs->d1ccipr);  in configure_clocks()
364 	writel(0x0, &regs->d2ccip1r);  in configure_clocks()
365 	writel(0x0, &regs->d2ccip2r);  in configure_clocks()
367 	/* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */  in configure_clocks()
376 	clrbits_le32(&regs->cr, RCC_CR_HSEON);  in configure_clocks()
377 	while ((readl(&regs->cr) & RCC_CR_HSERDY))  in configure_clocks()
381 	clrbits_le32(&regs->cr, RCC_CR_HSEBYP);  in configure_clocks()
383 	setbits_le32(&regs->cr, RCC_CR_HSEON);  in configure_clocks()
384 	while (!(readl(&regs->cr) & RCC_CR_HSERDY))  in configure_clocks()
388 	clrbits_le32(&regs->cr, RCC_CR_PLL1ON);  in configure_clocks()
389 	while ((readl(&regs->cr) & RCC_CR_PLL1RDY))  in configure_clocks()
392 	/* Select HSE as PLL clock source */  in configure_clocks()
395 	writel(pllckselr, &regs->pllckselr);  in configure_clocks()
397 	pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;  in configure_clocks()
398 	pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;  in configure_clocks()
399 	pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;  in configure_clocks()
400 	pll1divr |= (sys_pll_psc.divn - 1);  in configure_clocks()
401 	writel(pll1divr, &regs->pll1divr);  in configure_clocks()
407 	writel(pllcfgr, &regs->pllcfgr);  in configure_clocks()
410 	setbits_le32(&regs->cr, RCC_CR_PLL1ON);  in configure_clocks()
412 	/* set HPRE (/2) DI clk --> 125MHz */  in configure_clocks()
413 	clrsetbits_le32(&regs->d1cfgr, RCC_D1CFGR_HPRE_MASK,  in configure_clocks()
416 	/*  select PLL1 as system clock source (sys_ck)*/  in configure_clocks()
417 	clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);  in configure_clocks()
418 	while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)  in configure_clocks()
421 	/* sdram: use pll1_q as fmc_k clk */  in configure_clocks()
422 	clrsetbits_le32(&regs->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,  in configure_clocks()
433 	divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK;  in stm32_get_HSI_divider()
450 	[HSE] = "clk-hse",
451 	[LSE] = "clk-lse",
452 	[HSI] = "clk-hsi",
453 	[CSI] = "clk-csi",
454 	[I2S] = "clk-i2s",
455 	[TIMER] = "timer-clk"
460 	struct clk clk;  in stm32_get_rate()  local
468 	clk.id = 0;  in stm32_get_rate()
471 		pr_err("Can't find clk %s (%d)", name, ret);  in stm32_get_rate()
475 	ret = clk_request(fixed_clock_dev, &clk);  in stm32_get_rate()
477 		pr_err("Can't request %s clk (%d)", name, ret);  in stm32_get_rate()
486 	      divider, clk_get_rate(&clk));  in stm32_get_rate()
488 	return clk_get_rate(&clk) >> divider;  in stm32_get_rate()
505 	switch (readl(&regs->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {  in stm32_get_PLL1_rate()
527 	divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;  in stm32_get_PLL1_rate()
530 	divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;  in stm32_get_PLL1_rate()
532 	divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;  in stm32_get_PLL1_rate()
535 	divq1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;  in stm32_get_PLL1_rate()
538 	divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;  in stm32_get_PLL1_rate()
541 	fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;  in stm32_get_PLL1_rate()
565 	return -EINVAL;  in stm32_get_PLL1_rate()
571 	u32 d2cfgr = readl(&regs->d2cfgr);  in stm32_get_apb_psc()
593 	struct stm32_rcc_regs *regs = priv->rcc_base;  in stm32_get_timer_rate()
596 	if (readl(&regs->cfgr) & RCC_CFGR_TIMPRE)  in stm32_get_timer_rate()
629 static ulong stm32_clk_get_rate(struct clk *clk)  in stm32_clk_get_rate()  argument
631 	struct stm32_clk *priv = dev_get_priv(clk->dev);  in stm32_clk_get_rate()
632 	struct stm32_rcc_regs *regs = priv->rcc_base;  in stm32_clk_get_rate()
638 	u8 source, idx;  in stm32_clk_get_rate()  local
641 	 * get system clock (sys_ck) source  in stm32_clk_get_rate()
644 	source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK;  in stm32_clk_get_rate()
645 	switch (source) {  in stm32_clk_get_rate()
666 	debug("%s system clock: source = %d freq = %ld\n",  in stm32_clk_get_rate()
667 	      __func__, source, sysclk);  in stm32_clk_get_rate()
669 	d1cfgr = readl(&regs->d1cfgr);  in stm32_clk_get_rate()
684 	gate_offset = clk_map[clk->id].gate_offset;  in stm32_clk_get_rate()
686 	debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",  in stm32_clk_get_rate()
687 	      __func__, clk->id, gate_offset, sysclk);  in stm32_clk_get_rate()
712 		d3cfgr = readl(&regs->d3cfgr);  in stm32_clk_get_rate()
729 		switch (clk->id) {  in stm32_clk_get_rate()
750 		switch (clk->id) {  in stm32_clk_get_rate()
768 		return -EINVAL;  in stm32_clk_get_rate()
773 static int stm32_clk_enable(struct clk *clk)  in stm32_clk_enable()  argument
775 	struct stm32_clk *priv = dev_get_priv(clk->dev);  in stm32_clk_enable()
776 	struct stm32_rcc_regs *regs = priv->rcc_base;  in stm32_clk_enable()
779 	unsigned long clk_id = clk->id;  in stm32_clk_enable()
785 	      __func__, clk->id, gate_offset, gate_bit_index,  in stm32_clk_enable()
788 	setbits_le32(&regs->cr + (gate_offset / 4), BIT(gate_bit_index));  in stm32_clk_enable()
802 		return -EINVAL;  in stm32_clk_probe()
804 	priv->rcc_base = (struct stm32_rcc_regs *)addr;  in stm32_clk_probe()
815 	priv->pwr_regmap = syscon_get_regmap(syscon);  in stm32_clk_probe()
816 	if (!priv->pwr_regmap) {  in stm32_clk_probe()
818 		return -ENODEV;  in stm32_clk_probe()
826 static int stm32_clk_of_xlate(struct clk *clk,  in stm32_clk_of_xlate()  argument
829 	if (args->args_count != 1) {  in stm32_clk_of_xlate()
830 		debug("Invaild args_count: %d\n", args->args_count);  in stm32_clk_of_xlate()
831 		return -EINVAL;  in stm32_clk_of_xlate()
834 	if (args->args_count) {  in stm32_clk_of_xlate()
835 		clk->id = args->args[0];  in stm32_clk_of_xlate()
839 		 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)  in stm32_clk_of_xlate()
843 		if (clk->id >= KERN_BANK) {  in stm32_clk_of_xlate()
844 			clk->id -= KERN_BANK;  in stm32_clk_of_xlate()
845 			clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;  in stm32_clk_of_xlate()
847 			clk->id -= PERIF_BANK;  in stm32_clk_of_xlate()
850 		clk->id = 0;  in stm32_clk_of_xlate()
853 	debug("%s clk->id %ld\n", __func__, clk->id);  in stm32_clk_of_xlate()