Lines Matching +full:0 +full:x4000000
13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
25 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 MAS3_SX|MAS3_SW|MAS3_SR, 0,
28 0, 0, BOOKE_PAGESZ_4K, 0),
31 * TLB 0: 64M Non-cacheable, guarded
32 * 0xfc000000 56M unused
33 * 0xff800000 8M boot FLASH
35 * 0xfc000000 64M user flash
39 SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
41 0, 0, BOOKE_PAGESZ_64M, 1),
45 * 0x80000000 512M PCI1 MEM
46 * 0xa0000000 512M PCIe MEM
50 0, 1, BOOKE_PAGESZ_1G, 1),
54 * 0xe0000000 1M CCSRBAR
55 * 0xe2000000 8M PCI1 IO
56 * 0xe2800000 8M PCIe IO
60 0, 2, BOOKE_PAGESZ_64M, 1),
65 * 0xf0000000 64M LBC SDRAM First half
69 0, 3, BOOKE_PAGESZ_64M, 1),
73 * 0xf4000000 64M LBC SDRAM Second half
75 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
76 CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
78 0, 4, BOOKE_PAGESZ_64M, 1),
83 * 0xf8000000 1M 7-segment LED display
84 * 0xf8100000 1M User switches
85 * 0xf8300000 1M Board revision
86 * 0xf8b00000 1M EEPROM
90 0, 5, BOOKE_PAGESZ_16M, 1),
95 * 0xec000000 64M 64MB user FLASH
99 0, 6, BOOKE_PAGESZ_64M, 1),
103 * 0xef800000 4M 1st 1/2 8MB soldered FLASH
107 0, 6, BOOKE_PAGESZ_4M, 1),
111 * 0xefc00000 4M 2nd half 8MB soldered FLASH
113 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
114 CONFIG_SYS_ALT_FLASH + 0x400000,
116 0, 7, BOOKE_PAGESZ_4M, 1),