Lines Matching +full:0 +full:x00000019
14 #define MODE_MSK_FREE_RUN 0x00000001
15 #define MODE_VAL_FREE_RUN 0x00000000
16 #define MODE_MSK_STEP_UP 0x00000001
17 #define MODE_VAL_STEP_UP 0x00000000
20 #define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E
21 #define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004
22 #define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E
23 #define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008
24 #define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E
25 #define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C
28 #define MODE_MSK_BOOT_CA15 0x000000C0
29 #define MODE_VAL_BOOT_CA15 0x00000000
30 #define MODE_MSK_BOOT_CA7 0x000000C0
31 #define MODE_VAL_BOOT_CA7 0x00000040
32 #define MODE_MSK_BOOT_SH4 0x000000C0
33 #define MODE_VAL_BOOT_SH4 0x000000C0
36 #define MODE_MSK_JTAG_CORESIGHT 0xC0301C00
37 #define MODE_VAL_JTAG_CORESIGHT 0x00200000
38 #define MODE_MSK_JTAG_SH4 0xC0301C00
39 #define MODE_VAL_JTAG_SH4 0x00300000
42 #define MODE_MSK_DDR3_1600 0x00080000
43 #define MODE_VAL_DDR3_1600 0x00000000
44 #define MODE_MSK_DDR3_1333 0x00080000
45 #define MODE_VAL_DDR3_1333 0x00080000
48 #define MODE_MSK_PHY0_SATA0 0x01000000
49 #define MODE_VAL_PHY0_SATA0 0x00000000
50 #define MODE_MSK_PHY0_PCIE 0x01000000
51 #define MODE_VAL_PHY0_PCIE 0x01000000
54 #define MODE_MSK_PHY1_SATA1 0x00800000
55 #define MODE_VAL_PHY1_SATA1 0x00000000
56 #define MODE_MSK_PHY1_USB3 0x00800000
57 #define MODE_VAL_PHY1_USB3 0x00800000
98 #define MUX_MSK_VIN0_BT656 0x00001001
99 #define MUX_VAL_VIN0_BT656 0x00000000
101 #define MUX_MSK_VIN0_full 0x00001007
102 #define MUX_VAL_VIN0_full 0x00000002
104 #define MUX_MSK_VIN1_BT656 0x00000801
105 #define MUX_VAL_VIN1_BT656 0x00000800
107 #define MUX_MSK_VIN1_10bit 0x00000821
108 #define MUX_VAL_VIN1_10bit 0x00000800
110 #define MUX_MSK_VIN1_12bit 0x000008A1
111 #define MUX_VAL_VIN1_12bit 0x00000880
113 #define MUX_MSK_VIN2_BT656 0x00000007
114 #define MUX_VAL_VIN2_BT656 0x00000006
116 #define MUX_MSK_VIN2_withSYNC 0x000000A7
117 #define MUX_VAL_VIN2_withSYNC 0x00000086
119 #define MUX_MSK_VIN2_withFIELD 0x0000000F
120 #define MUX_VAL_VIN2_withFIELD 0x0000000E
122 #define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF
123 #define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E
125 #define MUX_MSK_VIN3_BT656 0x00000101
126 #define MUX_VAL_VIN3_BT656 0x00000100
128 #define MUX_MSK_VIN3_withFIELD 0x00000121
129 #define MUX_VAL_VIN3_withFIELD 0x00000120
131 #define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161
132 #define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120
134 #define MUX_MSK_AVB 0x00000003
135 #define MUX_VAL_AVB 0x00000000
137 #define MUX_MSK_QSPI_ONBOARD 0x00000019
138 #define MUX_VAL_QSPI_ONBOARD 0x00000000
140 #define MUX_MSK_QSPI_COMEXPRESS 0x00000019
141 #define MUX_VAL_QSPI_COMEXPRESS 0x00000010
143 #define MUX_MSK_I2C1 0x00000061
144 #define MUX_VAL_I2C1 0x00000060
146 #define MUX_MSK_IRQ3 0x00000101
147 #define MUX_VAL_IRQ3 0x00000000
149 #define MUX_MSK_SCIFA0_USB 0x00004081
150 #define MUX_VAL_SCIFA0_USB 0x00004000
152 #define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081
153 #define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000
155 #define MUX_MSK_SCIFA2 0x00002001
156 #define MUX_VAL_SCIFA2 0x00000000
158 #define MUX_MSK_ETH_ONBOARD 0x00000600
159 #define MUX_VAL_ETH_ONBOARD 0x00000000
161 #define MUX_MSK_ETH_COMEXPRESS 0x00000600
162 #define MUX_VAL_ETH_COMEXPRESS 0x00000400
164 #define MUX_MSK_SD0 0x00000801
165 #define MUX_VAL_SD0 0x00000000
167 #define MUX_MSK_SD2 0x00001001
168 #define MUX_VAL_SD2 0x00001000
170 #define MUX_MSK_PWM210 0x00002001
171 #define MUX_VAL_PWM210 0x00002000
173 #define HDMI_MSK 0x07
174 #define HDMI_OFF 0x00
175 #define HDMI_ONBOARD 0x07
176 #define HDMI_COMEXPRESS 0x05
177 #define HDMI_ONBOARD_NODDC 0x03
178 #define HDMI_COMEXPRESS_NODDC 0x01