Lines Matching +full:two +full:- +full:ethernet
2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
29 -------------------------------------------------------------------------
38 ------------------
39 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
40 processor cores with high-performance data path acceleration architecture
45 - Four e5500 cores, each with a private 256 KB L2 cache
46 - 256 KB shared L3 CoreNet platform cache (CPC)
47 - Interconnect CoreNet platform
48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
50 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
52 - Packet parsing, classification, and distribution
53 - Queue management for scheduling, packet sequencing, and congestion
55 - Cryptography Acceleration (SEC 5.0)
56 - RegEx Pattern Matching Acceleration (PME 2.2)
57 - IEEE Std 1588 support
58 - Hardware buffer management for buffer allocation and deallocation
59 - Ethernet interfaces
60 - Integrated 8-port Gigabit Ethernet switch (T1040 only)
61 - Four 1 Gbps Ethernet controllers
62 - Two RGMII interfaces or one RGMII and one MII interfaces
63 - High speed peripheral interfaces
64 - Four PCI Express 2.0 controllers running at up to 5 GHz
65 - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
66 - Upto two QSGMII interface
67 - Upto six SGMII interface supporting 1000 Mbps
68 - One SGMII interface supporting upto 2500 Mbps
69 - Additional peripheral interfaces
70 - Two USB 2.0 controllers with integrated PHY
71 - SD/eSDHC/eMMC
72 - eSPI controller
73 - Four I2C controllers
74 - Four UARTs
75 - Four GPIO controllers
76 - Integrated flash controller (IFC)
77 - LCD and HDMI interface (DIU) with 12 bit dual data rate
78 - TDM interface
79 - Multicore programmable interrupt controller (PIC)
80 - Two 8-channel DMA engines
81 - Single source clocking implementation
82 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
85 -------------------------
90 T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
91 Ethernet switch. Rest of the blocks are same as T1040
95 -------------------------
96 - SERDES Connections, 8 lanes information:
105 - DDR Controller
106 - Supports rates of up to 1600 MHz data-rate
107 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
108 - IFC/Local Bus
109 - NAND flash: 1GB 8-bit NAND flash
110 - NOR: 128MB 16-bit NOR Flash
111 - Ethernet
112 - Two on-board RGMII 10/100/1G ethernet ports.
113 - CPLD
114 - Clocks
115 - System and DDR clock (SYSCLK, “DDRCLK”)
116 - SERDES clocks
117 - Power Supplies
118 - USB
119 - Supports two USB 2.0 ports with integrated PHYs
120 - Two type A ports with 5V@1.5A per port.
121 - SDHC
122 - SDHC/SDXC connector
123 - SPI
124 - On-board 64MB SPI flash
125 - Other IO
126 - Two Serial ports
127 - Four I2C ports
130 -------------------------
131 - SERDES Connections, 8 lanes information:
137 - DDR Controller
138 - Supports rates of up to 1600 MHz data-rate
139 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
140 - IFC/Local Bus
141 - NAND flash: 1GB 8-bit NAND flash
142 - NOR: 128MB 16-bit NOR Flash
143 - Ethernet
144 - Two on-board RGMII 10/100/1G ethernet ports.
145 - CPLD
146 - Clocks
147 - System and DDR clock (SYSCLK, “DDRCLK”)
148 - SERDES clocks
149 - Video
150 - DIU supports video at up to 1280x1024x32bpp
151 - Power Supplies
152 - USB
153 - Supports two USB 2.0 ports with integrated PHYs
154 - Two type A ports with 5V@1.5A per port.
155 - SDHC
156 - SDHC/SDXC connector
157 - SPI
158 - On-board 64MB SPI flash
159 - Other IO
160 - Two Serial ports
161 - Four I2C ports
164 -----------
168 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
169 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
177 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
187 ---------------------
189 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
190 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
196 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
197 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
206 --------------------------------------------------------------
209 1. U-Boot environment variable hwconfig
228 ----------------------------------
231 U-Boot(768 KB) from flash to DDR.
232 Finally SPL transer control to U-Boot for futher booting.
235 - Executes within 256K
236 - No relocation required
238 Run time view of SPL framework during boot :-
239 -----------------------------------------------
241 -----------------------------------------------
244 -----------------------------------------------
246 -----------------------------------------------
248 -----------------------------------------------
250 -----------------------------------------------
252 -----------------------------------------------
253 U-Boot SPL | 0xFFFD8000 (160KB) |
254 -----------------------------------------------
257 ------------------------------------------
259 0x000000 0x0FFFFF U-Boot 1MB
260 0x180000 0x19FFFF U-Boot env 128KB
265 ------------------------------------------
267 0x008 2048 U-Boot 1MB
268 0x800 0024 U-Boot env 8KB
273 ------------------------------------------
275 0x000000 0x0FFFFF U-Boot 1MB
276 0x100000 0x101FFF U-Boot env 8KB
327 PBL-based image generation
334 By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
337 For SD-boot
353 For SPI-boot