1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
37  * Note that we need to byte-swap the value before it's written to the AD
78 	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;  in diu_set_pixel_clock()
79 	out_be32(&gur->clkdvdr, temp);			/* turn off clock */  in diu_set_pixel_clock()
80 	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));  in diu_set_pixel_clock()
92 	 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",  in platform_diu_init()
96 	 * In FCM mode, writes go to the NAND controller, which does not pass  in platform_diu_init()
98 	 * mode, since we don't care about what's behind the localbus any  in platform_diu_init()
132 	 * We know that the upper bits are 0 for 32-bit addressing, or 0xF for  in platform_diu_init()
133 	 * 36-bit addressing.  in platform_diu_init()
153 	temp = in_8(&pixis->brdcfg1);  in platform_diu_init()
163 		name = "Single-Link LVDS";  in platform_diu_init()
172 	out_8(&pixis->brdcfg1, temp);  in platform_diu_init()
175 	 * Enable PIXIS indirect access mode.  This is a hack that allows us to  in platform_diu_init()
179 	setbits_8(&pixis->csr, PX_CTL_ALTACC);  in platform_diu_init()
191 	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);  in platform_diu_init()
192 	pmuxcr = in_be32(&gur->pmuxcr);  in platform_diu_init()
198  * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
216 	/* Switch the muxes only if they're currently set to DIU mode */  in set_mux_to_lbc()
217 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in set_mux_to_lbc()
220 		 * In DIU mode, the PIXIS can only be accessed indirectly  in set_mux_to_lbc()
228 		/* Disable indirect PIXIS mode */  in set_mux_to_lbc()
232 		/* Set the chip mux to LBC mode, so that writes go to flash. */  in set_mux_to_lbc()
233 		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |  in set_mux_to_lbc()
235 		in_be32(&gur->pmuxcr);  in set_mux_to_lbc()
250  * set_mux_to_diu - re-enable the DIU muxing
258 	/* Set BR0 and BR1 to GPCM mode */  in set_mux_to_diu()
264 	/* Enable indirect PIXIS mode */  in set_mux_to_diu()
265 	setbits_8(&pixis->csr, PX_CTL_ALTACC);  in set_mux_to_diu()
272 	/* Set the chip mux to DIU mode. */  in set_mux_to_diu()
273 	out_be32(&gur->pmuxcr, pmuxcr);  in set_mux_to_diu()
274 	in_be32(&gur->pmuxcr);  in set_mux_to_diu()
278  * pixis_read - board-specific function to read from the PIXIS
281  * use PIXIS indirect mode if necessary.
287 	/* Use indirect mode if the mux is currently set to DIU mode */  in pixis_read()
288 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in pixis_read()
300  * pixis_write - board-specific function to write to the PIXIS
303  * use PIXIS indirect mode if necessary.
309 	/* Use indirect mode if the mux is currently set to DIU mode */  in pixis_write()
310 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in pixis_write()
314 		/* Do a read-back to ensure the write completed */  in pixis_write()
327 	 * in indirect mode, so switch to direct mode first.  in pixis_bank_reset()
331 	out_8(&pixis->vctl, 0);  in pixis_bank_reset()
332 	out_8(&pixis->vctl, 1);  in pixis_bank_reset()
339 void flash_write8(u8 value, void *addr)  in flash_write8()  argument
343 	__raw_writeb(value, addr);  in flash_write8()
346 		 * To ensure the post-write is completed to eLBC, software must  in flash_write8()
348 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write8()
352 		__raw_readb(addr);  in flash_write8()
357 void flash_write16(u16 value, void *addr)  in flash_write16()  argument
361 	__raw_writew(value, addr);  in flash_write16()
364 		 * To ensure the post-write is completed to eLBC, software must  in flash_write16()
366 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write16()
370 		__raw_readb(addr);  in flash_write16()
375 void flash_write32(u32 value, void *addr)  in flash_write32()  argument
379 	__raw_writel(value, addr);  in flash_write32()
382 		 * To ensure the post-write is completed to eLBC, software must  in flash_write32()
384 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write32()
388 		__raw_readb(addr);  in flash_write32()
393 void flash_write64(u64 value, void *addr)  in flash_write64()  argument
396 	uint32_t *p = addr;  in flash_write64()
410 		 * To ensure the post-write is completed to eLBC, software must  in flash_write64()
412 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  We  in flash_write64()
413 		 * read addr+4 because we just wrote to addr+4, so that's how we  in flash_write64()
418 		__raw_readb(addr + 4);  in flash_write64()
423 u8 flash_read8(void *addr)  in flash_read8()  argument
429 	ret = __raw_readb(addr);  in flash_read8()
436 u16 flash_read16(void *addr)  in flash_read16()  argument
442 	ret = __raw_readw(addr);  in flash_read16()
449 u32 flash_read32(void *addr)  in flash_read32()  argument
455 	ret = __raw_readl(addr);  in flash_read32()
462 u64 flash_read64(void *addr)  in flash_read64()  argument
469 	ret = *(volatile u64 *)addr;  in flash_read64()