1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
81 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);  in board_early_init_f()
85 	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);  in board_early_init_f()
86 	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);  in board_early_init_f()
97 	 * Remap Boot flash region to caching-inhibited  in board_early_init_r()
101 	/* Flush d-cache and invalidate i-cache of any FLASH data */  in board_early_init_r()
105 	if (flash_esel == -1) {  in board_early_init_r()
148 		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);  in config_board_mux()
157 		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,  in config_board_mux()
161 		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);  in config_board_mux()
164 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);  in config_board_mux()
165 		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);  in config_board_mux()
168 		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);  in config_board_mux()
186 		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);  in config_board_mux()
196 		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,  in config_board_mux()
276 	cpu = gd->arch.cpu;  in checkboard()
278 	printf("Board: %sRDB-PA, ", cpu->name);  in checkboard()
280 	printf("Board: %sRDB-PB, ", cpu->name);  in checkboard()
293 	val = (in_8(&cpld_data->pcba_ver) & 0xf);  in checkboard()
296 	val = in_8(&cpld_data->cpld_ver);  in checkboard()
299 	val = in_8(&cpld_data->rom_loc) & 0xf;  in checkboard()
336 	cpu = gd->arch.cpu;  in board_eth_init()
348 	if (cpu->soc_ver != SVR_P1014) {  in board_eth_init()
375 				"fsl,p1010-flexcan")) >= 0) {  in fdt_del_flexcan()
405 				"fsl,starlite-tdm")) >= 0) {  in fdt_del_tdm()
451 	cpu = gd->arch.cpu;  in ft_board_setup()
469 	if (cpu->soc_ver == SVR_P1014) {  in ft_board_setup()
490 		 * explicitly, defaultly spi_cs_sel to spi-flash instead of  in ft_board_setup()
506 		return -1;  in board_mmc_init()
523 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |  in misc_init_r()
529 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |  in misc_init_r()
531 		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |  in misc_init_r()
533 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);  in misc_init_r()
534 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);  in misc_init_r()
547 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);  in misc_init_r()