21 #define FLASH_CYCLE1    0x5555
22 #define FLASH_CYCLE2    0x2aaa
39 	ulong size = 0;  in flash_init()
40 	ulong fbase = 0;  in flash_init()
43 	flash_get_size((FPWV *) fbase, &flash_info[0]);  in flash_init()
44 	flash_get_offsets((ulong) fbase, &flash_info[0]);  in flash_init()
45 	fbase += flash_info[0].size;  in flash_init()
46 	size += flash_info[0].size;  in flash_init()
51 		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);  in flash_init()
62 		info->start[0] = base;  in flash_get_offsets()
63 		info->protect[0] = 0;  in flash_get_offsets()
67 			info->protect[i] = 0;  in flash_get_offsets()
96 	if (info->size > 0x100000) {  in flash_print_info()
101 		remainder = (info->size % 0x100000);  in flash_print_info()
116 	for (i = 0; i < info->sector_count; ++i) {  in flash_print_info()
117 		if ((i % 5) == 0)  in flash_print_info()
132 	addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA;	/* for Atmel, Intel ignores this */  in flash_get_size()
133 	addr[FLASH_CYCLE2] = (FPWV) 0x00550055;	/* for Atmel, Intel ignores this */  in flash_get_size()
134 	addr[FLASH_CYCLE1] = (FPWV) 0x00900090;	/* selects Intel or Atmel */  in flash_get_size()
136 	switch (addr[0] & 0xffff) {  in flash_get_size()
144 		info->sector_count = 0;  in flash_get_size()
145 		info->size = 0;  in flash_get_size()
147 		*addr = (FPW) 0x00F000F0;  in flash_get_size()
148 		return (0);	/* no or unknown flash  */  in flash_get_size()
160 	info->sector_count = 0;  in flash_get_size()
161 	info->size = 0;  in flash_get_size()
166 	*addr = (FPWV) 0x00F000F0;  in flash_get_size()
182 	int rcode = 0, flashtype = 0;  in flash_erase()
184 	if ((s_first < 0) || (s_first > s_last)) {  in flash_erase()
205 	prot = 0;  in flash_erase()
220 	start = get_timer(0);  in flash_erase()
223 		if (prot == 0) {  in flash_erase()
224 			addr = (FPWV *) info->start[0];  in flash_erase()
226 			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */  in flash_erase()
227 			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */  in flash_erase()
228 			addr[FLASH_CYCLE1] = 0x0080;	/* erase mode */  in flash_erase()
229 			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */  in flash_erase()
230 			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */  in flash_erase()
231 			*addr = 0x0030;	/* erase chip */  in flash_erase()
233 			count = 0;  in flash_erase()
234 			start = get_timer(0);  in flash_erase()
236 			while ((*addr & 0x0080) != 0x0080) {  in flash_erase()
237 				if (count++ > 0x10000) {  in flash_erase()
239 					count = 0;  in flash_erase()
244 					*addr = 0x00F0;	/* reset to read mode */  in flash_erase()
250 			*addr = 0x00F0;	/* reset to read mode */  in flash_erase()
257 			return 0;  in flash_erase()
265 		if (info->protect[sect] == 0) {	/* not protected */  in flash_erase()
272 			start = get_timer(0);  in flash_erase()
283 					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */  in flash_erase()
284 					base[FLASH_CYCLE2] = 0x0055;	/* unlock */  in flash_erase()
285 					base[FLASH_CYCLE1] = 0x0080;	/* erase mode */  in flash_erase()
286 					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */  in flash_erase()
287 					base[FLASH_CYCLE2] = 0x0055;	/* unlock */  in flash_erase()
288 					*addr = 0x0050;	/* erase sector */  in flash_erase()
293 					while ((*addr & 0x0080) != 0x0080) {  in flash_erase()
297 							*addr = 0x00F0;	/* reset to read mode */  in flash_erase()
304 					*addr = 0x00F0;	/* reset to read mode */  in flash_erase()
335 		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)  in write_buff()
347 		count = 0;  in write_buff()
350 		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)  in write_buff()
357 		if (count++ > 0x800) {  in write_buff()
359 			count = 0;  in write_buff()
365 		count = 0;  in write_buff()
368 		data = (data & 0x00FF) | (*src << 8);  in write_buff()
370 		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)  in write_buff()
376 		if (count++ > 0x800) {  in write_buff()
378 			count = 0;  in write_buff()
382 	if (cnt == 0)  in write_buff()
394  * 0 - OK
402 	int res = 0;		/* result, assume success */  in write_word()
415 	base[FLASH_CYCLE1] = (u8) 0x00AA00AA;	/* unlock */  in write_word()
416 	base[FLASH_CYCLE2] = (u8) 0x00550055;	/* unlock */  in write_word()
417 	base[FLASH_CYCLE1] = (u8) 0x00A000A0;	/* selects program mode */  in write_word()
425 	start = get_timer(0);  in write_word()
428 	while (res == 0  in write_word()
429 	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {  in write_word()
431 			*dest = (u8) 0x00F000F0;	/* reset bank */  in write_word()
436 	*dest++ = (u8) 0x00F000F0;	/* reset bank */  in write_word()
443 	static int p = 0;  in spin_wheel()
447 	(++p == 3) ? (p = 0) : 0;  in spin_wheel()