compulab/cm_t43/spl.c

29 	.emif_sdram_config_ext	= 0x0143,
34 	.sdram_config			= 0x638413B2,
35 	.ref_ctrl			= 0x00000C30,
36 	.sdram_tim1			= 0xEAAAD4DB,
37 	.sdram_tim2			= 0x266B7FDA,
38 	.sdram_tim3			= 0x107F8678,
39 	.read_idle_ctrl			= 0x00050000,
40 	.zq_config			= 0x50074BE4,
41 	.temp_alert_config		= 0x0,
42 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
43 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
44 	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
45 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
46 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
47 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
48 	.emif_rd_wr_exec_thresh		= 0x80000405,
49 	.emif_prio_class_serv_map	= 0x80000001,
50 	.emif_connect_id_serv_1_map	= 0x80000094,
51 	.emif_connect_id_serv_2_map	= 0x00000000,
52 	.emif_cos_config		= 0x000FFFFF
56 	0x00000000,
57 	0x00000044,
58 	0x00000044,
59 	0x00000046,
60 	0x00000046,
61 	0x00000000,
62 	0x00000059,
63 	0x00000077,
64 	0x00000093,
65 	0x000000A8,
66 	0x00000000,
67 	0x00000019,
68 	0x00000037,
69 	0x00000053,
70 	0x00000068,
71 	0x00000000,
72 	0x0,
73 	0x0,
74 	0x40000000,
75 	0x08102040
119 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);  in sdram_init()
120 	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);  in sdram_init()
121 	if (ram_size == 0x80000000 ||  in sdram_init()
122 	    ram_size == 0x40000000 ||  in sdram_init()
123 	    ram_size == 0x20000000)  in sdram_init()
126 	ddr3_emif_regs.sdram_config = 0x638453B2;  in sdram_init()
127 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);  in sdram_init()
128 	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);  in sdram_init()
129 	if (ram_size == 0x08000000)  in sdram_init()