Lines Matching refs:bit3
37 # bit3-0: 0 required
55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
76 # bit3-2: 3, Cs0size=1Gbit
96 # bit3-0: 0, Cmd=Normal SDRAM Mode
102 # bit3: 0, Burst Type (0 required)
126 # bit3: 1, MBUS Burst Chop disabled
138 # bit3-0: 0 required
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
161 # bit3-2: 0x0, CS0 hit selected
179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
189 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
194 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3