armadeus/apf27/apf27.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
87 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
88 					    * SDRAM: 0=1ck 1=2ck
90 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
103 #define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength 1=half
133 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
134 					    * SDRAM: 0=1ck 1=2ck
136 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
137 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
149 #define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength 1=half
179 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
180 					    * SDRAM: 0=1ck 1=2ck
182 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
183 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
195 #define ACFG_SDRAM_DRIVE_STRENGH	0  /* 0=Full-strength
276  * Default configuration for GPIOs and peripherals
402 	|((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28)	\
403 	|((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12)	\
404 	|((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
408 	(((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0)	\
409 	|((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6)	\
410 	|(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
411 	|(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
414 	|(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
418 	(((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0)	\
419 	|((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8)	\
420 	|((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16)	\
421 	|((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
430 	((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
439 	((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
445 				| (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
446 				| (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
456 	| (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
457 		ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
458 	| (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
460 		ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
461 	| (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
463 	| (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
464 		ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
465 	| (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
466 		ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
468 	| (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
469 		ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \